Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53268 )
Change subject: arch-arm, dev-arm: Move inSecureState helper to ISA class
......................................................................
arch-arm, dev-arm: Move inSecureState helper to ISA class
The helper function should be really part of the Arm ISA class
Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.hh
M src/arch/arm/pmu.cc
M src/arch/arm/utility.hh
M src/dev/arm/gic_v3_cpu_interface.cc
4 files changed, 38 insertions(+), 32 deletions(-)
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 645a765..b1aca70 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -846,13 +846,11 @@
if (miscRegInfo[reg][MISCREG_BANKED]) {
bool secure_reg = release->has(ArmExtension::SECURITY)
&&
!highestELIs64 &&
- inSecureState(miscRegs[MISCREG_SCR],
-
miscRegs[MISCREG_CPSR]);
+ inSecureState();
flat_idx += secure_reg ? 2 : 1;
} else {
flat_idx = snsBankedIndex64((MiscRegIndex)reg,
- !inSecureState(miscRegs[MISCREG_SCR],
- miscRegs[MISCREG_CPSR]));
+ !inSecureState());
}
}
return flat_idx;
@@ -953,8 +951,8 @@
// do additional S/NS flattenings if mapped to NS while in S
bool S = release->has(ArmExtension::SECURITY)
&& !highestELIs64 &&
- inSecureState(miscRegs[MISCREG_SCR],
- miscRegs[MISCREG_CPSR]);
+ inSecureState();
+
int lower = lookUpMiscReg[flat_idx].lower;
int upper = lookUpMiscReg[flat_idx].upper;
// upper == 0, which is CPSR, is not MISCREG_BANKED_CHILD
(no-op)
@@ -963,6 +961,26 @@
return std::make_pair(lower, upper);
}
+ bool
+ inSecureState() const
+ {
+ SCR scr = miscRegs[MISCREG_SCR];
+ CPSR cpsr = miscRegs[MISCREG_CPSR];
+
+ switch ((OperatingMode) (uint8_t) cpsr.mode) {
+ case MODE_MON:
+ case MODE_EL3T:
+ case MODE_EL3H:
+ return true;
+ case MODE_HYP:
+ case MODE_EL2T:
+ case MODE_EL2H:
+ return false;
+ default:
+ return !scr.ns;
+ }
+ }
+
unsigned getCurSveVecLenInBits() const;
unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *
128; }
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 57df5f6..6956eb0 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -491,10 +491,9 @@
assert(pmu.isa);
const PMEVTYPER_t filter(this->filter);
- const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
const ExceptionLevel el(currEL(cpsr));
- const bool secure(inSecureState(scr, cpsr));
+ const bool secure(pmu.isa->inSecureState());
switch (el) {
case EL0:
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 46dda3a..2155e8c 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -217,23 +217,6 @@
int computeAddrTop(ThreadContext *tc, bool selbit, bool isInstr,
TCR tcr, ExceptionLevel el);
-static inline bool
-inSecureState(SCR scr, CPSR cpsr)
-{
- switch ((OperatingMode) (uint8_t) cpsr.mode) {
- case MODE_MON:
- case MODE_EL3T:
- case MODE_EL3H:
- return true;
- case MODE_HYP:
- case MODE_EL2T:
- case MODE_EL2H:
- return false;
- default:
- return !scr.ns;
- }
-}
-
bool isSecureBelowEL3(ThreadContext *tc);
bool longDescFormatInUse(ThreadContext *tc);
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 4ae6b9b..a56cb66 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2333,13 +2333,7 @@
bool
Gicv3CPUInterface::inSecureState() const
{
- if (!gic->getSystem()->has(ArmExtension::SECURITY)) {
- return false;
- }
-
- CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
- SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR);
- return gem5::inSecureState(scr, cpsr);
+ return isa->inSecureState();
}
int
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ida0393a12426c8973a9b8171ec2922c2dcec9f5a
Gerrit-Change-Number: 53268
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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