Mahyar Samani has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53304 )
Change subject: stdlib: Removing SingleChannelMemory
......................................................................
stdlib: Removing SingleChannelMemory
This change removes the code base for SingleChannelMemory and
replaces it with MultiChannelMemory. muli_channel defines all
the classes that were defined by single_channel. Basically any
SingleChannelMemory could be thought of as a MultiChannelMemory
with 1 channel.
Change-Id: If96079d5f77be5a3ba26d2c2ddb98f5c60375cd8
---
M configs/example/gem5_library/riscv-fs.py
M configs/example/gem5_library/arm-hello.py
M tests/gem5/configs/boot_kvm_fork_run.py
M tests/gem5/configs/parsec_disk_run.py
M tests/gem5/configs/boot_kvm_switch_exit.py
M src/python/SConscript
M configs/example/gem5_library/x86-ubuntu-run.py
M tests/gem5/configs/simple_binary_run.py
D src/python/gem5/components/memory/single_channel.py
M tests/gem5/traffic_gen/test_memory_traffic_gen.py
10 files changed, 22 insertions(+), 153 deletions(-)
diff --git a/configs/example/gem5_library/arm-hello.py
b/configs/example/gem5_library/arm-hello.py
index 540a96b..8be714d 100644
--- a/configs/example/gem5_library/arm-hello.py
+++ b/configs/example/gem5_library/arm-hello.py
@@ -49,7 +49,7 @@
from gem5.resources.resource import Resource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
diff --git a/configs/example/gem5_library/riscv-fs.py
b/configs/example/gem5_library/riscv-fs.py
index f46a345..d79e3bf 100644
--- a/configs/example/gem5_library/riscv-fs.py
+++ b/configs/example/gem5_library/riscv-fs.py
@@ -43,7 +43,7 @@
from m5.objects import Root
from gem5.components.boards.riscv_board import RiscvBoard
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.cachehierarchies.classic.\
private_l1_private_l2_cache_hierarchy import (
diff --git a/configs/example/gem5_library/x86-ubuntu-run.py
b/configs/example/gem5_library/x86-ubuntu-run.py
index 1ab9f3a..95b1acd 100644
--- a/configs/example/gem5_library/x86-ubuntu-run.py
+++ b/configs/example/gem5_library/x86-ubuntu-run.py
@@ -46,7 +46,7 @@
from gem5.utils.requires import requires
from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
diff --git a/src/python/SConscript b/src/python/SConscript
index d210960..d457cf4 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -117,7 +117,6 @@
PySource('gem5.components.memory', 'gem5/components/memory/__init__.py')
PySource('gem5.components.memory', 'gem5/components/memory/abstract_memory_system.py')
PySource('gem5.components.memory', 'gem5/components/memory/dramsim_3.py')
-PySource('gem5.components.memory', 'gem5/components/memory/single_channel.py')
PySource('gem5.components.memory', 'gem5/components/memory/simple.py')
PySource('gem5.components.memory', 'gem5/components/memory/multi_channel.py')
PySource('gem5.components.memory.dram_interfaces',
diff --git a/src/python/gem5/components/memory/single_channel.py
b/src/python/gem5/components/memory/single_channel.py
deleted file mode 100644
index 11a0b15..0000000
--- a/src/python/gem5/components/memory/single_channel.py
+++ /dev/null
@@ -1,136 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All rights reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-"""Single channel "generic" DDR memory controllers
-"""
-
-from ..boards.abstract_board import AbstractBoard
-from .abstract_memory_system import AbstractMemorySystem
-from ...utils.override import overrides
-
-from m5.objects import AddrRange, DRAMInterface, MemCtrl, Port
-from m5.util.convert import toMemorySize
-
-from typing import List, Sequence, Tuple, Type, Optional
-
-
-class SingleChannelMemory(AbstractMemorySystem):
- """A simple implementation of a single channel memory system
-
- This class can take a DRAM Interface as a parameter to model many
different
- DDR memory systems.
- """
-
- def __init__(
- self,
- dram_interface_class: Type[DRAMInterface],
- size: Optional[str] = None,
- ):
- """
- :param dram_interface_class: The DRAM interface type to create with
- this memory controller
- :param size: Optionally specify the size of the DRAM controller's
- address space. By default, it starts at 0 and ends at the size
of
- the DRAM device specified
- """
- super().__init__()
-
- self._dram = dram_interface_class()
- if size:
- self._size = toMemorySize(size)
- else:
- self._size = self._get_dram_size(self._dram)
- self.mem_ctrl = MemCtrl(dram=self._dram)
-
- def _get_dram_size(self, dram: DRAMInterface) -> int:
- return (
- dram.device_size.value
- * dram.devices_per_rank.value
- * dram.ranks_per_channel.value
- )
-
- @overrides(AbstractMemorySystem)
- def incorporate_memory(self, board: AbstractBoard) -> None:
- pass
-
- @overrides(AbstractMemorySystem)
- def get_mem_ports(self) -> Tuple[Sequence[AddrRange], Port]:
- return [(self._dram.range, self.mem_ctrl.port)]
-
- @overrides(AbstractMemorySystem)
- def get_memory_controllers(self) -> List[MemCtrl]:
- return [self.mem_ctrl]
-
- @overrides(AbstractMemorySystem)
- def get_size(self) -> int:
- return self._size
-
- @overrides(AbstractMemorySystem)
- def set_memory_range(self, ranges: List[AddrRange]) -> None:
- if len(ranges) != 1 or ranges[0].size() != self._size:
- print(ranges[0].size())
- raise Exception(
- "Single channel memory controller requires a single range "
- "which matches the memory's size."
- )
- self.mem_ctrl.dram.range = ranges[0]
-
-
-from .dram_interfaces.ddr3 import DDR3_1600_8x8, DDR3_2133_8x8
-from .dram_interfaces.ddr4 import DDR4_2400_8x8
-from .dram_interfaces.lpddr3 import LPDDR3_1600_1x32
-from .dram_interfaces.hbm import HBM_1000_4H_1x128
-
-# Enumerate all of the different DDR memory systems we support
-def SingleChannelDDR3_1600(size: Optional[str] = None) ->
AbstractMemorySystem:
- """
- A single channel memory system using a single DDR3_1600_8x8 based DIMM
- """
- return SingleChannelMemory(DDR3_1600_8x8, size)
-
-
-def SingleChannelDDR3_2133(size: Optional[str] = None) ->
AbstractMemorySystem:
- """
- A single channel memory system using a single DDR3_2133_8x8 based DIMM
- """
- return SingleChannelMemory(DDR3_2133_8x8, size)
-
-
-def SingleChannelDDR4_2400(size: Optional[str] = None) ->
AbstractMemorySystem:
- """
- A single channel memory system using a single DDR4_2400_8x8 based DIMM
- """
- return SingleChannelMemory(DDR4_2400_8x8, size)
-
-
-def SingleChannelLPDDR3_1600(
- size: Optional[str] = None,
-) -> AbstractMemorySystem:
- return SingleChannelMemory(LPDDR3_1600_1x32, size)
-
-
-def SingleChannelHBM(size: Optional[str] = None) -> AbstractMemorySystem:
- return SingleChannelMemory(HBM_1000_4H_1x128, size)
diff --git a/tests/gem5/configs/boot_kvm_fork_run.py
b/tests/gem5/configs/boot_kvm_fork_run.py
index 14d6a4b..97b61dc 100644
--- a/tests/gem5/configs/boot_kvm_fork_run.py
+++ b/tests/gem5/configs/boot_kvm_fork_run.py
@@ -46,7 +46,7 @@
from gem5.components.boards.x86_board import X86Board
from gem5.coherence_protocol import CoherenceProtocol
from gem5.isas import ISA
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
diff --git a/tests/gem5/configs/boot_kvm_switch_exit.py
b/tests/gem5/configs/boot_kvm_switch_exit.py
index 68651eb..a2540a7 100644
--- a/tests/gem5/configs/boot_kvm_switch_exit.py
+++ b/tests/gem5/configs/boot_kvm_switch_exit.py
@@ -36,7 +36,7 @@
from gem5.components.boards.x86_board import X86Board
from gem5.coherence_protocol import CoherenceProtocol
from gem5.isas import ISA
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
diff --git a/tests/gem5/configs/parsec_disk_run.py
b/tests/gem5/configs/parsec_disk_run.py
index c65be10..66a64ac 100644
--- a/tests/gem5/configs/parsec_disk_run.py
+++ b/tests/gem5/configs/parsec_disk_run.py
@@ -42,7 +42,7 @@
from gem5.resources.resource import Resource
from gem5.components.boards.x86_board import X86Board
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_switchable_processor import (
SimpleSwitchableProcessor,
)
diff --git a/tests/gem5/configs/simple_binary_run.py
b/tests/gem5/configs/simple_binary_run.py
index b41f26d..3f7cb89 100644
--- a/tests/gem5/configs/simple_binary_run.py
+++ b/tests/gem5/configs/simple_binary_run.py
@@ -36,7 +36,7 @@
from gem5.resources.resource import Resource
from gem5.components.boards.simple_board import SimpleBoard
from gem5.components.cachehierarchies.classic.no_cache import NoCache
-from gem5.components.memory.single_channel import SingleChannelDDR3_1600
+from gem5.components.memory.multi_channel import SingleChannelDDR3_1600
from gem5.components.processors.simple_processor import SimpleProcessor
from gem5.components.processors.cpu_types import CPUTypes
diff --git a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
index 4b97601..c2283e9 100644
--- a/tests/gem5/traffic_gen/test_memory_traffic_gen.py
+++ b/tests/gem5/traffic_gen/test_memory_traffic_gen.py
@@ -135,15 +135,6 @@
)
create_single_core_tests(
- "gem5.components.memory.single_channel",
- common_memory_classes,
-)
-create_dual_core_tests(
- "gem5.components.memory.single_channel",
- common_memory_classes,
-)
-
-create_single_core_tests(
"gem5.components.memory.multi_channel",
common_memory_classes + multi_memory_classes,
)
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53304
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If96079d5f77be5a3ba26d2c2ddb98f5c60375cd8
Gerrit-Change-Number: 53304
Gerrit-PatchSet: 1
Gerrit-Owner: Mahyar Samani <msam...@ucdavis.edu>
Gerrit-MessageType: newchange
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