[gem5-dev] Change in gem5/gem5[develop]: mem: incMissCount should be cache line based

[Huang Jiasen (Gerrit) via gem5-dev]

Huang Jiasen has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/53383 )

Change subject: mem: incMissCount should be cache line based
......................................................................

mem: incMissCount should be cache line based

Change-Id: I0ced667255b3672fc3960c8187092d674958e17d
---
M src/mem/cache/mshr.cc
M src/mem/cache/mshr.hh
M src/mem/cache/base.cc
3 files changed, 46 insertions(+), 1 deletion(-)



diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index dc21151..7608704 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -522,6 +522,9 @@
         mshrQueue.markPending(mshr);
         schedMemSideSendEvent(clockEdge() + pkt->payloadDelay);
     } else {
+        // Reset the reference counter once the entry is released.
+        mshr->resetRefCnt();
+
         // while we deallocate an mshr from the queue we still have to
         // check the isFull condition before and after as we might
         // have been using the reserved entries already
@@ -1406,7 +1409,16 @@
     // Can't satisfy access normally... either no block (blk == nullptr)
     // or have block but need writable

-    incMissCount(pkt);
+    MSHR *mshr = mshrQueue.findMatch(pkt->getBlockAddr(blkSize),
+                                    pkt->isSecure());
+    if (mshr) {
+        mshr->incRefCnt();
+        if (mshr->getRefCnt() < 2) {
+            incHitCount(pkt);
+        }
+    } else {
+        incMissCount(pkt);
+    }

     lat = calculateAccessLatency(blk, pkt->headerDelay, tag_latency);

diff --git a/src/mem/cache/mshr.cc b/src/mem/cache/mshr.cc
index 6aaaf9e..54b6193 100644
--- a/src/mem/cache/mshr.cc
+++ b/src/mem/cache/mshr.cc
@@ -68,6 +68,7 @@
         targets(name + ".targets"),
         deferredTargets(name + ".deferredTargets")
 {
+    refCnt = 0;
 }

 MSHR::TargetList::TargetList(const std::string &name)
diff --git a/src/mem/cache/mshr.hh b/src/mem/cache/mshr.hh
index a9deec6..e6c731a 100644
--- a/src/mem/cache/mshr.hh
+++ b/src/mem/cache/mshr.hh
@@ -80,8 +80,25 @@
     template<typename Entry>
     friend class Queue;
     friend class MSHRQueue;
+    friend class BaseCache;

   private:
+    /**
+     * Increase refCnt.
+     */
+    void incRefCnt() const {
+        MSHR* ptr = const_cast<MSHR*>(this);
+        ptr->refCnt++;
+    }
+    /**
+     * Reset refCnt.
+     */
+    void resetRefCnt() const {
+        MSHR* ptr = const_cast<MSHR*>(this);
+        ptr->refCnt = 0;
+    }
+    /** Accumulated hit record to the same cache line */
+    int refCnt;

     /** Flag set by downstream caches */
     bool downstreamPending;
@@ -119,6 +136,12 @@
     bool postDowngrade;

   public:
+    /**
+     * Get refCnt.
+     */
+    int getRefCnt() {
+        return refCnt;
+    }

     /** Track if we sent this as a whole line write or not */
     bool wasWholeLineWrite;

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0ced667255b3672fc3960c8187092d674958e17d
Gerrit-Change-Number: 53383
Gerrit-PatchSet: 1
Gerrit-Owner: Huang Jiasen <jiasen....@alibaba-inc.com>
Gerrit-MessageType: newchange
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