Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53624 )
Change subject: arch-arm, dev-arm: Add currEL function to the ISA class
......................................................................
arch-arm, dev-arm: Add currEL function to the ISA class
This utility is strictly ISA related. We are still keeping the
version accepting the TC as an argument; this is just
wrapping the ISA call.
In this way we are simplifying life for ISA devices, which have
a reference to the ISA object rather than a reference to the TC
Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/isa.hh
M src/arch/arm/pmu.cc
M src/arch/arm/utility.cc
M src/arch/arm/utility.hh
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
7 files changed, 50 insertions(+), 35 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f9e2976..02af0bc 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -629,7 +629,7 @@
miscRegName[misc_reg]);
}
#endif
- misc_reg = redirectRegVHE(tc, misc_reg);
+ misc_reg = redirectRegVHE(misc_reg);
switch (unflattenMiscReg(misc_reg)) {
case MISCREG_HCR:
@@ -1006,7 +1006,7 @@
miscRegName[misc_reg], val);
}
#endif
- misc_reg = redirectRegVHE(tc, misc_reg);
+ misc_reg = redirectRegVHE(misc_reg);
switch (unflattenMiscReg(misc_reg)) {
case MISCREG_CPACR:
@@ -2555,6 +2555,14 @@
}
}
+ExceptionLevel
+ISA::currEL() const
+{
+ CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
+
+ return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
+}
+
unsigned
ISA::getCurSveVecLenInBits() const
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 696097c..2afcc51 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -859,10 +859,10 @@
* HCR_EL2.E2H is enabled and executing at EL2
*/
int
- redirectRegVHE(ThreadContext * tc, int misc_reg)
+ redirectRegVHE(int misc_reg)
{
const HCR hcr = readMiscRegNoEffect(MISCREG_HCR_EL2);
- if (hcr.e2h == 0x0 || currEL(tc) != EL2)
+ if (hcr.e2h == 0x0 || currEL() != EL2)
return misc_reg;
SCR scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
bool sec_el2 = scr.eel2 &&
release->has(ArmExtension::FEAT_SEL2);
@@ -961,6 +961,11 @@
/** Return true if the PE is in Secure state */
bool inSecureState() const;
+ /**
+ * Returns the current Exception Level (EL) of the ISA object
+ */
+ ExceptionLevel currEL() const;
+
unsigned getCurSveVecLenInBits() const;
unsigned getCurSveVecLenInBitsAtReset() const { return sveVL *
128; }
diff --git a/src/arch/arm/pmu.cc b/src/arch/arm/pmu.cc
index 6956eb0..f0ab978 100644
--- a/src/arch/arm/pmu.cc
+++ b/src/arch/arm/pmu.cc
@@ -491,8 +491,7 @@
assert(pmu.isa);
const PMEVTYPER_t filter(this->filter);
- const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
- const ExceptionLevel el(currEL(cpsr));
+ const ExceptionLevel el(pmu.isa->currEL());
const bool secure(pmu.isa->inSecureState());
switch (el) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d24f470..2a98eea 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -124,6 +124,13 @@
return opModeIs64((OperatingMode) (uint8_t) cpsr.mode);
}
+ExceptionLevel
+currEL(const ThreadContext *tc)
+{
+ return static_cast<ArmISA::ISA *>(
+ const_cast<ThreadContext *>(tc)->getIsaPtr())->currEL();
+}
+
bool
longDescFormatInUse(ThreadContext *tc)
{
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 9514eb0..0e5f3bb 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -108,13 +108,11 @@
bool inAArch64(ThreadContext *tc);
-static inline ExceptionLevel
-currEL(const ThreadContext *tc)
-{
- CPSR cpsr = tc->readMiscRegNoEffect(MISCREG_CPSR);
-
- return opModeToEL((OperatingMode)(uint8_t)cpsr.mode);
-}
+/**
+ * Returns the current Exception Level (EL) of the
+ * provided ThreadContext
+ */
+ExceptionLevel currEL(const ThreadContext *tc);
inline ExceptionLevel
currEL(CPSR cpsr)
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index a56cb66..6093e86 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2336,29 +2336,10 @@
return isa->inSecureState();
}
-int
+ExceptionLevel
Gicv3CPUInterface::currEL() const
{
- CPSR cpsr = isa->readMiscRegNoEffect(MISCREG_CPSR);
- bool is_64 = opModeIs64((OperatingMode)(uint8_t) cpsr.mode);
-
- if (is_64) {
- return (ExceptionLevel)(uint8_t) cpsr.el;
- } else {
- switch (cpsr.mode) {
- case MODE_USER:
- return 0;
-
- case MODE_HYP:
- return 2;
-
- case MODE_MON:
- return 3;
-
- default:
- return 1;
- }
- }
+ return isa->currEL();
}
bool
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index 7058d66..eb16602 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -309,7 +309,7 @@
void activateIRQ(uint32_t intid, Gicv3::GroupId group);
void generateSGI(RegVal val, Gicv3::GroupId group);
- int currEL() const;
+ ArmISA::ExceptionLevel currEL() const;
void deactivateIRQ(uint32_t intid, Gicv3::GroupId group);
void dropPriority(Gicv3::GroupId group);
uint64_t eoiMaintenanceInterruptStatus() const;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Icb286d174538b50962d31aa3f6e836b3c791dc1c
Gerrit-Change-Number: 53624
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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