Huang Jiasen has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53643 )
Change subject: mem-cache: Fixed the bug of resetting to zero addr for
WriteAllocator when MSHR is not whole line writable
......................................................................
mem-cache: Fixed the bug of resetting to zero addr for WriteAllocator when
MSHR is not whole line writable
Change-Id: I15f45a4a8fc1746429809a8e02228bcc062aad85
---
M src/mem/cache/base.cc
M src/mem/cache/base.hh
2 files changed, 18 insertions(+), 1 deletion(-)
diff --git a/src/mem/cache/base.cc b/src/mem/cache/base.cc
index dc21151..4032b84 100644
--- a/src/mem/cache/base.cc
+++ b/src/mem/cache/base.cc
@@ -1813,7 +1813,7 @@
mshrQueue.delay(mshr, delay);
return false;
} else {
- writeAllocator->reset();
+ writeAllocator->reset(tgt_pkt->getAddr());
}
} else {
writeAllocator->resetDelay(mshr->blkAddr);
diff --git a/src/mem/cache/base.hh b/src/mem/cache/base.hh
index 0dc64e1..14e73db 100644
--- a/src/mem/cache/base.hh
+++ b/src/mem/cache/base.hh
@@ -1418,6 +1418,14 @@
nextAddr = 0;
}
+ /** Reset to the pop address in the target list of MSHR
+ * if MSHR is not whole line writable
+ */
+ void reset(const Addr& tgt_addr) {
+ mode = WriteMode::ALLOCATE;
+ nextAddr = tgt_addr;
+ }
+
/**
* Access whether we need to delay the current write.
*
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/53643
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I15f45a4a8fc1746429809a8e02228bcc062aad85
Gerrit-Change-Number: 53643
Gerrit-PatchSet: 1
Gerrit-Owner: Huang Jiasen <jiasen....@alibaba-inc.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
