Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/53328 )
Change subject: fastmodel: CortexR52 implements setResetAddr interface
......................................................................
fastmodel: CortexR52 implements setResetAddr interface
Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53328
Maintainer: Bobby Bruce <bbr...@ucdavis.edu>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Earl Ou <shunhsin...@google.com>
---
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
8 files changed, 45 insertions(+), 2 deletions(-)
Approvals:
Earl Ou: Looks good to me, approved
Bobby Bruce: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index f5817f9..85a4c2a 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -79,6 +79,12 @@
set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
}
+void
+CortexR52::setResetAddr(Addr addr, bool secure)
+{
+ evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
Port &
CortexR52::getPort(const std::string &if_name, PortID idx)
{
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
index c43052b..76c7d33 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.hh
@@ -72,6 +72,8 @@
void setCluster(CortexR52Cluster *_cluster, int _num);
+ void setResetAddr(Addr addr, bool secure = false) override;
+
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
};
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 5dcda4e..720f1cc 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -66,7 +66,7 @@
void
ScxEvsCortexR52<Types>::setResetAddr(int core, Addr addr, bool secure)
{
- panic("Not implemented for R52.");
+ this->corePins[core]->cfgvectable.set_state(0, addr);
}
template <class Types>
@@ -78,7 +78,8 @@
amba(evs->amba[cpu], name + ".amba", -1),
core_reset(name + ".core_reset", 0),
poweron_reset(name + ".poweron_reset", 0),
- halt(name + ".halt", 0)
+ halt(name + ".halt", 0),
+ cfgvectable((name + "cfgvectable").c_str())
{
for (int i = 0; i < Evs::PpiCount; i++) {
ppis.emplace_back(
@@ -87,6 +88,7 @@
core_reset.signal_out.bind(evs->core_reset[cpu]);
poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
halt.signal_out.bind(evs->halt[cpu]);
+ cfgvectable.bind(evs->cfgvectable[cpu]);
}
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index a616a4d..fa9d7fe 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -79,6 +79,8 @@
struct CorePins
{
using CoreInt = IntSinkPin<CorePins>;
+ template <typename T>
+ using SignalInitiator = amba_pv::signal_master_port<T>;
std::string name;
Evs *evs;
@@ -107,6 +109,8 @@
SignalSender core_reset;
SignalSender poweron_reset;
SignalSender halt;
+
+ SignalInitiator<uint64_t> cfgvectable;
};
std::vector<std::unique_ptr<CorePins>> corePins;
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
index a15fe74..36f3279 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -59,6 +59,9 @@
self.ppi_0 => core.extppi_in_0;
self.spi => core.spi_in;
+
+ // Core reset addrs.
+ self.cfgvectable => core.cfgvectable;
}
properties
@@ -74,6 +77,7 @@
slave port<Signal> poweron_reset[1];
slave port<Signal> halt[1];
slave port<Signal> top_reset;
+ slave port<Value_64> cfgvectable[1];
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
index 9b992a4..492d289 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -60,6 +60,9 @@
self.ppi_1 => core.extppi_in_1;
self.spi => core.spi_in;
+
+ // Core reset addrs.
+ self.cfgvectable => core.cfgvectable;
}
properties
@@ -75,6 +78,7 @@
slave port<Signal> poweron_reset[2];
slave port<Signal> halt[2];
slave port<Signal> top_reset;
+ slave port<Value_64> cfgvectable[2];
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
index 18619b9..ed4837c 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
@@ -61,6 +61,9 @@
self.ppi_2 => core.extppi_in_2;
self.spi => core.spi_in;
+
+ // Core reset addrs.
+ self.cfgvectable => core.cfgvectable;
}
properties
@@ -76,6 +79,7 @@
slave port<Signal> poweron_reset[3];
slave port<Signal> halt[3];
slave port<Signal> top_reset;
+ slave port<Value_64> cfgvectable[3];
slave port<ExportedClockRateControl> clock_rate_s
{
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
index d22079f..73680b1 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
@@ -62,6 +62,9 @@
self.ppi_3 => core.extppi_in_3;
self.spi => core.spi_in;
+
+ // Core reset addrs.
+ self.cfgvectable => core.cfgvectable;
}
properties
@@ -77,6 +80,7 @@
slave port<Signal> poweron_reset[4];
slave port<Signal> halt[4];
slave port<Signal> top_reset;
+ slave port<Value_64> cfgvectable[4];
slave port<ExportedClockRateControl> clock_rate_s
{
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I45da1c1538430061cc89f666cb02aa5fe77abcba
Gerrit-Change-Number: 53328
Gerrit-PatchSet: 2
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: Bobby Bruce <bbr...@ucdavis.edu>
Gerrit-Reviewer: Earl Ou <shunhsin...@google.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabebl...@google.com>
Gerrit-Reviewer: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-CC: Philip Metzler <cpm...@google.com>
Gerrit-MessageType: merged
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