Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/53803 )
Change subject: arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu
......................................................................
arch-gcn3,gpu-compute: Move TLB to common folder in amdgpu
This TLB is more of an "APU" TLB than anything GCN3 specific. It can be
used with either GCN3 or Vega. With this change, VEGA_X86 builds and one
can run binaries with Vega ISA code using the same steps as GCN3 but
building the Vega ISA instead.
Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c
---
M src/arch/amdgpu/gcn3/SConscript
M src/gpu-compute/compute_unit.cc
M src/gpu-compute/shader.cc
R src/arch/amdgpu/common/X86GPUTLB.py
M src/gpu-compute/fetch_unit.cc
R src/arch/amdgpu/common/tlb.cc
R src/arch/amdgpu/common/tlb.hh
M src/arch/amdgpu/gcn3/gpu_isa.hh
R src/arch/amdgpu/common/tlb_coalescer.cc
R src/arch/amdgpu/common/tlb_coalescer.hh
10 files changed, 23 insertions(+), 10 deletions(-)
diff --git a/src/arch/amdgpu/gcn3/X86GPUTLB.py
b/src/arch/amdgpu/common/X86GPUTLB.py
similarity index 96%
rename from src/arch/amdgpu/gcn3/X86GPUTLB.py
rename to src/arch/amdgpu/common/X86GPUTLB.py
index 1c7f1d0..b5f3387 100644
--- a/src/arch/amdgpu/gcn3/X86GPUTLB.py
+++ b/src/arch/amdgpu/common/X86GPUTLB.py
@@ -39,7 +39,7 @@
class X86GPUTLB(ClockedObject):
type = 'X86GPUTLB'
cxx_class = 'gem5::X86ISA::GpuTLB'
- cxx_header = 'arch/amdgpu/gcn3/tlb.hh'
+ cxx_header = 'arch/amdgpu/common/tlb.hh'
size = Param.Int(64, "TLB size (number of entries)")
assoc = Param.Int(64, "TLB associativity")
@@ -63,7 +63,7 @@
class TLBCoalescer(ClockedObject):
type = 'TLBCoalescer'
cxx_class = 'gem5::TLBCoalescer'
- cxx_header = 'arch/amdgpu/gcn3/tlb_coalescer.hh'
+ cxx_header = 'arch/amdgpu/common/tlb_coalescer.hh'
probesPerCycle = Param.Int(2, "Number of TLB probes per cycle")
coalescingWindow = Param.Int(1, "Permit coalescing across that many
ticks")
diff --git a/src/arch/amdgpu/gcn3/tlb.cc b/src/arch/amdgpu/common/tlb.cc
similarity index 99%
rename from src/arch/amdgpu/gcn3/tlb.cc
rename to src/arch/amdgpu/common/tlb.cc
index a6280da..e108a0b 100644
--- a/src/arch/amdgpu/gcn3/tlb.cc
+++ b/src/arch/amdgpu/common/tlb.cc
@@ -32,7 +32,7 @@
*
*/
-#include "arch/amdgpu/gcn3/tlb.hh"
+#include "arch/amdgpu/common/tlb.hh"
#include <cmath>
#include <cstring>
diff --git a/src/arch/amdgpu/gcn3/tlb.hh b/src/arch/amdgpu/common/tlb.hh
similarity index 100%
rename from src/arch/amdgpu/gcn3/tlb.hh
rename to src/arch/amdgpu/common/tlb.hh
diff --git a/src/arch/amdgpu/gcn3/tlb_coalescer.cc
b/src/arch/amdgpu/common/tlb_coalescer.cc
similarity index 99%
rename from src/arch/amdgpu/gcn3/tlb_coalescer.cc
rename to src/arch/amdgpu/common/tlb_coalescer.cc
index 9b53db8..507d0e2 100644
--- a/src/arch/amdgpu/gcn3/tlb_coalescer.cc
+++ b/src/arch/amdgpu/common/tlb_coalescer.cc
@@ -31,7 +31,7 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
-#include "arch/amdgpu/gcn3/tlb_coalescer.hh"
+#include "arch/amdgpu/common/tlb_coalescer.hh"
#include <cstring>
diff --git a/src/arch/amdgpu/gcn3/tlb_coalescer.hh
b/src/arch/amdgpu/common/tlb_coalescer.hh
similarity index 99%
rename from src/arch/amdgpu/gcn3/tlb_coalescer.hh
rename to src/arch/amdgpu/common/tlb_coalescer.hh
index afe12c9..22f311c 100644
--- a/src/arch/amdgpu/gcn3/tlb_coalescer.hh
+++ b/src/arch/amdgpu/common/tlb_coalescer.hh
@@ -39,7 +39,7 @@
#include <string>
#include <vector>
-#include "arch/amdgpu/gcn3/tlb.hh"
+#include "arch/amdgpu/common/tlb.hh"
#include "arch/generic/tlb.hh"
#include "arch/x86/isa.hh"
#include "arch/x86/pagetable.hh"
diff --git a/src/arch/amdgpu/gcn3/SConscript
b/src/arch/amdgpu/gcn3/SConscript
index e8e0002..eb309c4 100644
--- a/src/arch/amdgpu/gcn3/SConscript
+++ b/src/arch/amdgpu/gcn3/SConscript
@@ -39,15 +39,11 @@
Return()
if env['TARGET_GPU_ISA'] == 'gcn3':
- SimObject('X86GPUTLB.py', sim_objects=['X86GPUTLB', 'TLBCoalescer'])
-
Source('decoder.cc')
Source('insts/gpu_static_inst.cc')
Source('insts/instructions.cc')
Source('insts/op_encodings.cc')
Source('isa.cc')
Source('registers.cc')
- Source('tlb.cc')
- Source('tlb_coalescer.cc')
DebugFlag('GCN3', 'Debug flag for GCN3 GPU ISA')
diff --git a/src/arch/amdgpu/gcn3/gpu_isa.hh
b/src/arch/amdgpu/gcn3/gpu_isa.hh
index 205f097..26cbc5c 100644
--- a/src/arch/amdgpu/gcn3/gpu_isa.hh
+++ b/src/arch/amdgpu/gcn3/gpu_isa.hh
@@ -37,8 +37,8 @@
#include <array>
#include <type_traits>
+#include "arch/amdgpu/common/tlb.hh"
#include "arch/amdgpu/gcn3/gpu_registers.hh"
-#include "arch/amdgpu/gcn3/tlb.hh"
#include "gpu-compute/dispatcher.hh"
#include "gpu-compute/hsa_queue_entry.hh"
#include "gpu-compute/misc.hh"
diff --git a/src/gpu-compute/compute_unit.cc
b/src/gpu-compute/compute_unit.cc
index feef552..761d37b 100644
--- a/src/gpu-compute/compute_unit.cc
+++ b/src/gpu-compute/compute_unit.cc
@@ -35,6 +35,7 @@
#include <limits>
+#include "arch/amdgpu/common/tlb.hh"
#include "base/output.hh"
#include "debug/GPUDisp.hh"
#include "debug/GPUExec.hh"
diff --git a/src/gpu-compute/fetch_unit.cc b/src/gpu-compute/fetch_unit.cc
index 437a48d..fed9cb5 100644
--- a/src/gpu-compute/fetch_unit.cc
+++ b/src/gpu-compute/fetch_unit.cc
@@ -33,6 +33,7 @@
#include "gpu-compute/fetch_unit.hh"
+#include "arch/amdgpu/common/tlb.hh"
#include "base/bitfield.hh"
#include "debug/GPUFetch.hh"
#include "debug/GPUPort.hh"
diff --git a/src/gpu-compute/shader.cc b/src/gpu-compute/shader.cc
index ad18d01..4d71ca0 100644
--- a/src/gpu-compute/shader.cc
+++ b/src/gpu-compute/shader.cc
@@ -35,6 +35,7 @@
#include <limits>
+#include "arch/amdgpu/common/tlb.hh"
#include "base/chunk_generator.hh"
#include "debug/GPUAgentDisp.hh"
#include "debug/GPUDisp.hh"
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c92bcd0379a18628dc05cb5af070bdc7e692c7c
Gerrit-Change-Number: 53803
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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