Yu-hsin Wang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/54065 )
Change subject: fastmodel: Add a common reset controller for IrisCpu
......................................................................
fastmodel: Add a common reset controller for IrisCpu
The reset controller provides a register interface to config RVBAR and
ability to reset the core.
Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa
---
M src/arch/arm/fastmodel/iris/Iris.py
A src/arch/arm/fastmodel/iris/reset_controller.cc
A src/arch/arm/fastmodel/iris/reset_controller.hh
M src/arch/arm/fastmodel/iris/SConscript
4 files changed, 240 insertions(+), 0 deletions(-)
diff --git a/src/arch/arm/fastmodel/iris/Iris.py
b/src/arch/arm/fastmodel/iris/Iris.py
index 4979715..bcdfecb 100644
--- a/src/arch/arm/fastmodel/iris/Iris.py
+++ b/src/arch/arm/fastmodel/iris/Iris.py
@@ -43,6 +43,8 @@
from m5.objects.BaseISA import BaseISA
from m5.objects.BaseTLB import BaseTLB
from m5.objects.BaseMMU import BaseMMU
+from m5.objects.Device import BasicPioDevice
+from m5.objects.IntPin import IntSourcePin
class IrisTLB(BaseTLB):
type = 'IrisTLB'
@@ -100,3 +102,12 @@
def createInterruptController(self):
self.interrupts = [ IrisInterrupts() for i in
range(self.numThreads) ]
+
+class IrisResetController(BasicPioDevice):
+ type = 'IrisResetController'
+ cxx_class = 'gem5::Iris::ResetController'
+ cxx_header = 'arch/arm/fastmodel/iris/reset_controller.hh'
+
+ cpu = Param.IrisBaseCPU('target cpu')
+ reset = IntSourcePin('reset pin')
+ halt = IntSourcePin('halt pin')
diff --git a/src/arch/arm/fastmodel/iris/SConscript
b/src/arch/arm/fastmodel/iris/SConscript
index 6635ca0..f611e1a 100644
--- a/src/arch/arm/fastmodel/iris/SConscript
+++ b/src/arch/arm/fastmodel/iris/SConscript
@@ -36,3 +36,5 @@
Source('tlb.cc')
Source('thread_context.cc')
+
+Source('reset_controller.cc')
diff --git a/src/arch/arm/fastmodel/iris/reset_controller.cc
b/src/arch/arm/fastmodel/iris/reset_controller.cc
new file mode 100644
index 0000000..8decf39
--- /dev/null
+++ b/src/arch/arm/fastmodel/iris/reset_controller.cc
@@ -0,0 +1,128 @@
+/*
+ * Copyright 2021 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "arch/arm/fastmodel/iris/reset_controller.hh"
+
+#include "base/logging.hh"
+
+namespace gem5
+{
+namespace Iris
+{
+
+ResetController::CorePins::CorePins(const std::string &module_name)
+ : reset(module_name + ".reset", 0, this),
+ halt(module_name + ".halt", 0, this)
+{}
+
+ResetController::Registers::Registers(
+ const std::string &module_name, BaseCPU *c, CorePins *p)
+ : RegisterBankLE(module_name, 0), cpu(c), pins(p),
+ nsrvbar(module_name + ".nsrvbar"),
+ rvbar(module_name + ".rvbar"),
+ reset(module_name + ".reset"),
+ halt(module_name + ".halt")
+{
+ panic_if(cpu == nullptr, "ResetController needs a target cpu.");
+ nsrvbar.writer(
+ [this] (auto ®, auto val)
+ {
+ cpu->setResetAddr(val, false);
+ });
+ rvbar.writer(
+ [this] (auto ®, auto val)
+ {
+ cpu->setResetAddr(val, true);
+ });
+ reset.writer(
+ [this] (auto ®, auto val)
+ {
+ if (!pins->reset.isConnected()) {
+ warn_once("%s is not connected.", pins->reset.name());
+ return;
+ }
+
+ if (val) pins->reset.raise();
+ else pins->reset.lower();
+ });
+ halt.writer(
+ [this] (auto ®, auto val)
+ {
+ if (!pins->halt.isConnected()) {
+ warn_once("%s is not connected.", pins->halt.name());
+ return;
+ }
+
+ if (val) pins->halt.raise();
+ else pins->halt.lower();
+ });
+
+ addRegisters({
+ nsrvbar,
+ rvbar,
+ reset,
+ halt,
+ });
+}
+
+ResetController::ResetController(const IrisResetControllerParams &p)
+ : BasicPioDevice(p, 0x20),
+ pins(p.name + ".pins"),
+ registers(p.name + ".registers", p.cpu, &pins)
+{}
+
+Tick
+ResetController::read(PacketPtr pkt)
+{
+ pkt->makeResponse();
+ return pioDelay;
+}
+
+Tick
+ResetController::write(PacketPtr pkt)
+{
+ pkt->makeResponse();
+ size_t size = pkt->getSize();
+ if (size != 4 && size != 8) {
+ pkt->setBadAddress();
+ } else {
+ auto addr = pkt->getAddr() - pioAddr;
+ registers.write(addr, pkt->getPtr<void>(), size);
+ }
+ return pioDelay;
+}
+
+Port &
+ResetController::getPort(const std::string &if_name, PortID idx)
+{
+ if (if_name == "reset") return pins.reset;
+ else if (if_name == "halt") return pins.halt;
+ return BasicPioDevice::getPort(if_name, idx);
+}
+
+} // namespace Iris
+} // namespace gem5
diff --git a/src/arch/arm/fastmodel/iris/reset_controller.hh
b/src/arch/arm/fastmodel/iris/reset_controller.hh
new file mode 100644
index 0000000..ffff2f3
--- /dev/null
+++ b/src/arch/arm/fastmodel/iris/reset_controller.hh
@@ -0,0 +1,87 @@
+/*
+ * Copyright 2021 Google, Inc.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __ARCH_ARM_FASTMODEL_IRIS_RESET_CONTROLLER_HH__
+#define __ARCH_ARM_FASTMODEL_IRIS_RESET_CONTROLLER_HH__
+
+#include <string>
+
+#include "arch/arm/fastmodel/iris/cpu.hh"
+#include "dev/intpin.hh"
+#include "dev/io_device.hh"
+#include "dev/reg_bank.hh"
+#include "mem/packet_access.hh"
+#include "params/IrisResetController.hh"
+
+namespace gem5
+{
+
+namespace Iris
+{
+
+class ResetController : public BasicPioDevice
+{
+ private:
+ struct CorePins
+ {
+ using CoreInt = IntSourcePin<CorePins>;
+ CoreInt reset;
+ CoreInt halt;
+
+ explicit CorePins(const std::string &);
+ };
+
+ class Registers : public RegisterBankLE
+ {
+ private:
+ BaseCPU *cpu;
+ CorePins *pins;
+
+ Register64 nsrvbar;
+ Register64 rvbar;
+ Register32 reset;
+ Register32 halt;
+
+ public:
+ Registers(const std::string &, BaseCPU *, CorePins *);
+ };
+
+ CorePins pins;
+ Registers registers;
+
+ public:
+ explicit ResetController(const IrisResetControllerParams &);
+
+ Tick read(PacketPtr pkt) override;
+ Tick write(PacketPtr pkt) override;
+ Port & getPort(const std::string &if_name, PortID) override;
+};
+
+} // namespace Iris
+} // namespace gem5
+
+#endif // __ARCH_ARM_FASTMODEL_IRIS_RESET_CONTROLLER_HH__
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa
Gerrit-Change-Number: 54065
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-MessageType: newchange
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