Huang Jiasen has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/54364 )
Change subject: mem-cache: Set prefetch bit if the blk comes from Prefetch
only.
......................................................................
mem-cache: Set prefetch bit if the blk comes from Prefetch only.
Original logic setting prefetch inside serviceMSHRTargets
did not exclude the blks that both came from CORE and Prefetch
Change-Id: Iab56b9266eb64baf972b160774aca0823faea458
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54364
Reviewed-by: Daniel Carvalho <oda...@yahoo.com.br>
Maintainer: Daniel Carvalho <oda...@yahoo.com.br>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/mem/cache/noncoherent_cache.cc
M src/mem/cache/cache.cc
2 files changed, 37 insertions(+), 4 deletions(-)
Approvals:
Daniel Carvalho: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
index 3c24343..466aeec 100644
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -693,11 +693,16 @@
bool is_invalidate = pkt->isInvalidate() &&
!mshr->wasWholeLineWrite;
+ bool from_core = false;
+ bool from_pref = false;
+
MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
for (auto &target: targets) {
Packet *tgt_pkt = target.pkt;
switch (target.source) {
case MSHR::Target::FromCPU:
+ from_core = true;
+
Tick completion_time;
// Here we charge on completion_time the delay of the xbar if
the
// packet comes from it, charged on headerDelay.
@@ -852,8 +857,8 @@
case MSHR::Target::FromPrefetcher:
assert(tgt_pkt->cmd == MemCmd::HardPFReq);
- if (blk)
- blk->setPrefetched();
+ from_pref = true;
+
delete tgt_pkt;
break;
@@ -882,6 +887,10 @@
}
}
+ if (blk && !from_core && from_pref) {
+ blk->setPrefetched();
+ }
+
maintainClusivity(targets.hasFromCache, blk);
if (blk && blk->isValid()) {
diff --git a/src/mem/cache/noncoherent_cache.cc
b/src/mem/cache/noncoherent_cache.cc
index 314025f..9e95a20 100644
--- a/src/mem/cache/noncoherent_cache.cc
+++ b/src/mem/cache/noncoherent_cache.cc
@@ -245,6 +245,9 @@
// First offset for critical word first calculations
const int initial_offset = mshr->getTarget()->pkt->getOffset(blkSize);
+ bool from_core = false;
+ bool from_pref = false;
+
MSHR::TargetList targets = mshr->extractServiceableTargets(pkt);
for (auto &target: targets) {
Packet *tgt_pkt = target.pkt;
@@ -254,6 +257,8 @@
// handle deferred requests comming from a cache or core
// above
+ from_core = true;
+
Tick completion_time;
// Here we charge on completion_time the delay of the xbar if
the
// packet comes from it, charged on headerDelay.
@@ -292,8 +297,7 @@
// attached to this cache
assert(tgt_pkt->cmd == MemCmd::HardPFReq);
- if (blk)
- blk->setPrefetched();
+ from_pref = true;
// We have filled the block and the prefetcher does not
// require responses.
@@ -307,6 +311,10 @@
}
}
+ if (blk && !from_core && from_pref) {
+ blk->setPrefetched();
+ }
+
// Reponses are filling and bring in writable blocks, therefore
// there should be no deferred targets and all the non-deferred
// targets are now serviced.
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iab56b9266eb64baf972b160774aca0823faea458
Gerrit-Change-Number: 54364
Gerrit-PatchSet: 5
Gerrit-Owner: Huang Jiasen <jiasen....@alibaba-inc.com>
Gerrit-Reviewer: Daniel Carvalho <oda...@yahoo.com.br>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Huang Jiasen <jiasen....@alibaba-inc.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Nikos Nikoleris <nikos.nikole...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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