Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55463 )
Change subject: arch-vega: Free dest registers in non-memory Load DS insts
......................................................................
arch-vega: Free dest registers in non-memory Load DS insts
Ported from https://gem5-review.googlesource.com/c/public/gem5/+/48019:
Certain DS insts are classfied as Loads, but don't actually go through
the memory pipeline. However, any instruction classified as a load
marks its destination registers as free in the memory pipeline.
Because these instructions didn't use the memory pipeline, they
never freed their destination registers, which led to a deadlock.
This patch explicitly calls the function used to free the destination
registers in the execute() method of those Load instructions that
don't use the memory pipeline.
Change-Id: I8231217a79661ca6acc837b2ab4931b946049a1a
---
M src/arch/amdgpu/vega/insts/instructions.cc
1 file changed, 49 insertions(+), 0 deletions(-)
diff --git a/src/arch/amdgpu/vega/insts/instructions.cc
b/src/arch/amdgpu/vega/insts/instructions.cc
index 56ccc3d..4ecff1b 100644
--- a/src/arch/amdgpu/vega/insts/instructions.cc
+++ b/src/arch/amdgpu/vega/insts/instructions.cc
@@ -35467,6 +35467,15 @@
}
vdst.write();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_PERMUTE_B32 class methods ---
@@ -35541,6 +35550,15 @@
}
vdst.write();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_BPERMUTE_B32 class methods ---
@@ -35615,6 +35633,15 @@
}
vdst.write();
+
+ /**
+ * This is needed because we treat this instruction as a load
+ * but it's not an actual memory request.
+ * Without this, the destination register never gets marked as
+ * free, leading to a possible deadlock
+ */
+ wf->computeUnit->vrf[wf->simdId]->
+ scheduleWriteOperandsFromLoad(wf, gpuDynInst);
} // execute
// --- Inst_DS__DS_ADD_U64 class methods ---
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8231217a79661ca6acc837b2ab4931b946049a1a
Gerrit-Change-Number: 55463
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-MessageType: newchange
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