Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55608 )
Change subject: arch-arm: Avoid Gic write side effect with blockIntUpdate
......................................................................
arch-arm: Avoid Gic write side effect with blockIntUpdate
When trasferring the state between two GICs (essentially
writing architectural registers) an interrupt might be posted
by the model. We don't want this to happen as the GIC might
be in an inconsistent state. We therefore disable side effects
by relying on the blockIntUpdate method.
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I0e5a86551705254ebacb81b7b358470faad0230c
---
M src/dev/arm/gic_v3.hh
M src/dev/arm/gic_v3_distributor.cc
M src/dev/arm/base_gic.hh
M src/dev/arm/gic_v2.cc
M src/dev/arm/gic_v3_redistributor.cc
M src/dev/arm/gic_v3_cpu_interface.cc
6 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/src/dev/arm/base_gic.hh b/src/dev/arm/base_gic.hh
index 7100f51..63b8679 100644
--- a/src/dev/arm/base_gic.hh
+++ b/src/dev/arm/base_gic.hh
@@ -131,6 +131,16 @@
virtual bool supportsVersion(GicVersion version) = 0;
protected: // GIC state transfer
+
+ /**
+ * When trasferring the state between two GICs (essentially
+ * writing architectural registers) an interrupt might be posted
+ * by the model. We don't want this to happen as the GIC might
+ * be in an inconsistent state. We therefore disable side effects
+ * by relying on the blockIntUpdate method.
+ */
+ virtual bool blockIntUpdate() const { return false; }
+
virtual void copyGicState(BaseGicRegisters* from,
BaseGicRegisters* to) = 0;
diff --git a/src/dev/arm/gic_v2.cc b/src/dev/arm/gic_v2.cc
index 9a2e246..2ea48f7 100644
--- a/src/dev/arm/gic_v2.cc
+++ b/src/dev/arm/gic_v2.cc
@@ -738,6 +738,9 @@
void
GicV2::updateIntState(int hint)
{
+ if (blockIntUpdate())
+ return;
+
for (int cpu = 0; cpu < sys->threads.size(); cpu++) {
if (!cpuEnabled(cpu))
continue;
diff --git a/src/dev/arm/gic_v3.hh b/src/dev/arm/gic_v3.hh
index 37e0367..963beff 100644
--- a/src/dev/arm/gic_v3.hh
+++ b/src/dev/arm/gic_v3.hh
@@ -58,6 +58,7 @@
protected:
friend class Gicv3CPUInterface;
friend class Gicv3Redistributor;
+ friend class Gicv3Distributor;
Gicv3Distributor * distributor;
std::vector<Gicv3Redistributor *> redistributors;
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index 6093e86..393adde 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -2032,6 +2032,9 @@
void
Gicv3CPUInterface::update()
{
+ if (gic->blockIntUpdate())
+ return;
+
bool signal_IRQ = false;
bool signal_FIQ = false;
@@ -2066,6 +2069,9 @@
void
Gicv3CPUInterface::virtualUpdate()
{
+ if (gic->blockIntUpdate())
+ return;
+
bool signal_IRQ = false;
bool signal_FIQ = false;
int lr_idx = getHPPVILR();
diff --git a/src/dev/arm/gic_v3_distributor.cc
b/src/dev/arm/gic_v3_distributor.cc
index 75c3df5..aff6b94 100644
--- a/src/dev/arm/gic_v3_distributor.cc
+++ b/src/dev/arm/gic_v3_distributor.cc
@@ -1085,6 +1085,9 @@
void
Gicv3Distributor::update()
{
+ if (gic->blockIntUpdate())
+ return;
+
// Find the highest priority pending SPI
for (int int_id = Gicv3::SGI_MAX + Gicv3::PPI_MAX; int_id < itLines;
int_id++) {
diff --git a/src/dev/arm/gic_v3_redistributor.cc
b/src/dev/arm/gic_v3_redistributor.cc
index 8d4c29b..0d8c7ff 100644
--- a/src/dev/arm/gic_v3_redistributor.cc
+++ b/src/dev/arm/gic_v3_redistributor.cc
@@ -804,6 +804,9 @@
void
Gicv3Redistributor::update()
{
+ if (gic->blockIntUpdate())
+ return;
+
for (int int_id = 0; int_id < Gicv3::SGI_MAX + Gicv3::PPI_MAX;
int_id++) {
Gicv3::GroupId int_group = getIntGroup(int_id);
bool group_enabled = distributor->groupEnabled(int_group);
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55608
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0e5a86551705254ebacb81b7b358470faad0230c
Gerrit-Change-Number: 55608
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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