[gem5-dev] Change in gem5/gem5[develop]: arch-arm: Templatize set/getGicReg to support 64bit accesses

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/55613 )

Change subject: arch-arm: Templatize set/getGicReg to support 64bit accesses
......................................................................

arch-arm: Templatize set/getGicReg to support 64bit accesses

In Gicv2, every distributor/cpu interface register is read/written
with 32bit accesses.
The Gicv3 KVM APIs follow the same pattern for distributor and
redistributors; the system register implementation of the cpu interface
in Gicv3 requires 64bit read/writes instead [1]

We now explicitly select the Gic register size via a template
parameter.

[1]:
https://www.kernel.org/doc/html/latest/virt/kvm/devices/arm-vgic-v3.html

Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Change-Id: I471037179bf10e163baccf655cc1492bdfeae17f
---
M src/arch/arm/kvm/gic.cc
M src/arch/arm/kvm/gic.hh
2 files changed, 37 insertions(+), 11 deletions(-)



diff --git a/src/arch/arm/kvm/gic.cc b/src/arch/arm/kvm/gic.cc
index abc92e5..33a3f61 100644
--- a/src/arch/arm/kvm/gic.cc
+++ b/src/arch/arm/kvm/gic.cc
@@ -101,10 +101,11 @@
     vm.setIRQLine(line, high);
 }

-uint32_t
+template <typename Ret>
+Ret
 KvmKernelGic::getGicReg(unsigned group, unsigned vcpu, unsigned offset)
 {
-    uint64_t reg;
+    Ret reg;

     assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
     const uint64_t attr(
@@ -112,14 +113,15 @@
         (offset << KVM_DEV_ARM_VGIC_OFFSET_SHIFT));

     kdev.getAttrPtr(group, attr, &reg);
-    return (uint32_t) reg;
+    return reg;
 }

+template <typename Arg>
 void
 KvmKernelGic::setGicReg(unsigned group, unsigned vcpu, unsigned offset,
-                          unsigned value)
+                        Arg value)
 {
-    uint64_t reg = value;
+    Arg reg = value;

     assert(vcpu <= KVM_ARM_IRQ_VCPU_MASK);
     const uint64_t attr(
@@ -133,7 +135,7 @@
 KvmKernelGic::readDistributor(ContextID ctx, Addr daddr)
 {
     auto vcpu = vm.contextIdToVCpuId(ctx);
-    return getGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr);
+    return getGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu,  
daddr);
 }

 uint32_t
@@ -146,14 +148,14 @@
 KvmKernelGic::readCpu(ContextID ctx, Addr daddr)
 {
     auto vcpu = vm.contextIdToVCpuId(ctx);
-    return getGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
+    return getGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr);
 }

 void
 KvmKernelGic::writeDistributor(ContextID ctx, Addr daddr, uint32_t data)
 {
     auto vcpu = vm.contextIdToVCpuId(ctx);
-    setGicReg(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
+    setGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_DIST_REGS, vcpu, daddr, data);
 }

 void
@@ -166,7 +168,7 @@
 KvmKernelGic::writeCpu(ContextID ctx, Addr daddr, uint32_t data)
 {
     auto vcpu = vm.contextIdToVCpuId(ctx);
-    setGicReg(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
+    setGicReg<uint32_t>(KVM_DEV_ARM_VGIC_GRP_CPU_REGS, vcpu, daddr, data);
 }

 KvmKernelGicV2::KvmKernelGicV2(KvmVM &_vm,
diff --git a/src/arch/arm/kvm/gic.hh b/src/arch/arm/kvm/gic.hh
index 49edc8e..4ee048d 100644
--- a/src/arch/arm/kvm/gic.hh
+++ b/src/arch/arm/kvm/gic.hh
@@ -144,7 +144,8 @@
      * @param vcpu CPU id within KVM
      * @param offset register offset
      */
-    uint32_t getGicReg(unsigned group, unsigned vcpu, unsigned offset);
+    template <typename Ret>
+    Ret getGicReg(unsigned group, unsigned vcpu, unsigned offset);

     /**
      * Set value of GIC register "from" a cpu
@@ -154,8 +155,9 @@
      * @param offset register offset
      * @param value value to set register to
      */
+    template <typename Arg>
     void setGicReg(unsigned group, unsigned vcpu, unsigned offset,
-                   unsigned value);
+                   Arg value);

     /** KVM VM in the parent system */
     KvmVM &vm;

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I471037179bf10e163baccf655cc1492bdfeae17f
Gerrit-Change-Number: 55613
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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