Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/55692 )
Change subject: arch-x86: Implement interrupts in real mode.
......................................................................
arch-x86: Implement interrupts in real mode.
Software interrupts had been implemented earlier. This implements
hardware interrupt vectoring for real mode.
Change-Id: I92397514cdf64c3218175dd6cffd5931cc85d95b
---
M src/arch/x86/isa/insts/romutil.py
M src/arch/x86/faults.cc
2 files changed, 66 insertions(+), 1 deletion(-)
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 6c696c7..54fcade 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -72,7 +72,10 @@
if (m5reg.mode == LongMode) {
entry = extern_label_longModeInterrupt;
} else {
- entry = extern_label_legacyModeInterrupt;
+ if (m5reg.submode == RealMode)
+ entry = extern_label_realModeInterrupt;
+ else
+ entry = extern_label_legacyModeInterrupt;
}
tc->setIntReg(INTREG_MICRO(1), vector);
Addr cs_base = tc->readMiscRegNoEffect(MISCREG_CS_EFF_BASE);
diff --git a/src/arch/x86/isa/insts/romutil.py
b/src/arch/x86/isa/insts/romutil.py
index fd06197..847b9c4 100644
--- a/src/arch/x86/isa/insts/romutil.py
+++ b/src/arch/x86/isa/insts/romutil.py
@@ -216,4 +216,54 @@
halt
eret
};
+
+def rom
+{
+ extern realModeInterrupt:
+
+ # t1 - The vector.
+ # t2 - The old CS.
+ # t7 - The old RIP.
+ # t3 - RFLAGS
+ # t4 - The new CS.
+ # t5 - The new RIP.
+
+ rdsel t2, cs, dataSize=8
+ rflags t3, dataSize=8
+
+ ld t4, idtr, [4, t1, t0], 2, dataSize=2, addressSize=2
+ ld t5, idtr, [4, t1, t0], dataSize=2, addressSize=2
+
+ # Make sure pushes after the first will also work.
+ cda ss, [1, t0, rsp], -4, dataSize=2, addressSize=2
+ cda ss, [1, t0, rsp], -6, dataSize=2, addressSize=2
+
+ # Push the low 16 bits of RFLAGS.
+ st t3, ss, [1, t0, rsp], -2, dataSize=2, addressSize=2
+ # Push CS.
+ st t2, ss, [1, t0, rsp], -4, dataSize=2, addressSize=2
+ # Push the old RIP.
+ st t7, ss, [1, t0, rsp], -6, dataSize=2, addressSize=2
+
+ # Update RSP.
+ subi rsp, rsp, 6, dataSize=2
+
+ # Set the new CS selector.
+ wrsel cs, t4, dataSize=2
+ # Make sure there isn't any junk in the upper bits of the base.
+ mov t4, t0, t4, dataSize=2
+ # Compute and set CS base.
+ slli t4, t4, 4, dataSize=8
+ wrbase cs, t4, dataSize=8
+
+ # If IF or TF are set, we want to flip them.
+ limm t6, "(TFBit | IFBit)", dataSize=8
+ and t6, t6, t3, dataSize=8
+ wrflags t3, t6, dataSize=8
+
+ # Set the new RIP.
+ wrip t5, t0, dataSize=2
+
+ eret
+};
'''
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/55692
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I92397514cdf64c3218175dd6cffd5931cc85d95b
Gerrit-Change-Number: 55692
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
