Tiago Muck has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/41860 )
Change subject: mem-ruby: fix SimpleNetwork WeightBased routing
......................................................................
mem-ruby: fix SimpleNetwork WeightBased routing
Individual link weights are propagated to the routing algorithms and
WeightBased routing now uses this information to select the output
link when multiple routing options exist.
JIRA: https://gem5.atlassian.net/browse/GEM5-920
Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Signed-off-by: Tiago Mück <[email protected]>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/41860
Maintainer: Jason Lowe-Power <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/mem/ruby/network/simple/PerfectSwitch.cc
M src/mem/ruby/network/simple/PerfectSwitch.hh
M src/mem/ruby/network/simple/SimpleNetwork.cc
M src/mem/ruby/network/simple/Switch.cc
M src/mem/ruby/network/simple/Switch.hh
M src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
M src/mem/ruby/network/simple/routing/WeightBased.cc
M src/mem/ruby/network/simple/routing/WeightBased.hh
8 files changed, 53 insertions(+), 18 deletions(-)
Approvals:
Tiago Muck: Looks good to me, approved
Jason Lowe-Power: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.cc
b/src/mem/ruby/network/simple/PerfectSwitch.cc
index 154e491..19e1523 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.cc
+++ b/src/mem/ruby/network/simple/PerfectSwitch.cc
@@ -95,13 +95,15 @@
void
PerfectSwitch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- const PortDirection &dst_inport)
+ const PortDirection &dst_inport,
+ int link_weight)
{
// Add to routing unit
m_switch->getRoutingUnit().addOutPort(m_out.size(),
out,
routing_table_entry,
- dst_inport);
+ dst_inport,
+ link_weight);
m_out.push_back(out);
}
diff --git a/src/mem/ruby/network/simple/PerfectSwitch.hh
b/src/mem/ruby/network/simple/PerfectSwitch.hh
index d6c836b..41e9448 100644
--- a/src/mem/ruby/network/simple/PerfectSwitch.hh
+++ b/src/mem/ruby/network/simple/PerfectSwitch.hh
@@ -79,7 +79,8 @@
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- const PortDirection &dst_inport);
+ const PortDirection &dst_inport,
+ int link_weight);
int getInLinks() const { return m_in.size(); }
int getOutLinks() const { return m_out.size(); }
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc
b/src/mem/ruby/network/simple/SimpleNetwork.cc
index c30bd79..ec3a25e 100644
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -120,7 +120,8 @@
m_fromNetQueues[local_dest].resize(num_vnets, nullptr);
m_switches[src]->addOutPort(m_fromNetQueues[local_dest],
- routing_table_entry[0],
simple_link->m_latency,
+ routing_table_entry[0],
+ simple_link->m_latency, 0,
simple_link->m_bw_multiplier);
}
@@ -147,6 +148,7 @@
m_switches[dest]->addInPort(simple_link->m_buffers);
m_switches[src]->addOutPort(simple_link->m_buffers,
routing_table_entry[0],
simple_link->m_latency,
+ simple_link->m_weight,
simple_link->m_bw_multiplier,
dst_inport);
// Maitain a global list of buffers (used for functional accesses only)
diff --git a/src/mem/ruby/network/simple/Switch.cc
b/src/mem/ruby/network/simple/Switch.cc
index 8c0b229..fd43910 100644
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -85,7 +85,8 @@
void
Switch::addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- Cycles link_latency, int bw_multiplier,
+ Cycles link_latency, int link_weight,
+ int bw_multiplier,
PortDirection dst_inport)
{
const std::vector<int> &physical_vnets_channels =
@@ -122,7 +123,7 @@
// Hook the queues to the PerfectSwitch
perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry,
- dst_inport);
+ dst_inport, link_weight);
// Hook the queues to the Throttle
throttles.back().addLinks(intermediateBuffers, out);
diff --git a/src/mem/ruby/network/simple/Switch.hh
b/src/mem/ruby/network/simple/Switch.hh
index 70e5340..39a9716 100644
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -92,7 +92,7 @@
void addInPort(const std::vector<MessageBuffer*>& in);
void addOutPort(const std::vector<MessageBuffer*>& out,
const NetDest& routing_table_entry,
- Cycles link_latency, int bw_multiplier,
+ Cycles link_latency, int link_weight, int
bw_multiplier,
PortDirection dst_inport = "");
void resetStats();
diff --git a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
index 20f27f3..9ebf59d 100644
--- a/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
+++ b/src/mem/ruby/network/simple/routing/BaseRoutingUnit.hh
@@ -69,7 +69,8 @@
virtual void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction) = 0;
+ const PortDirection &direction,
+ int link_weight) = 0;
struct RouteInfo
{
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.cc
b/src/mem/ruby/network/simple/routing/WeightBased.cc
index 7db4665..a63b0fa 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.cc
+++ b/src/mem/ruby/network/simple/routing/WeightBased.cc
@@ -60,13 +60,15 @@
WeightBased::addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction)
+ const PortDirection &direction,
+ int link_weight)
{
gem5_assert(link_id == m_links.size());
m_links.emplace_back(new LinkInfo{link_id,
routing_table_entry,
m_out_buffer,
- static_cast<int>(link_id)});
+ 0, link_weight});
+ sortLinks();
}
void
@@ -81,7 +83,7 @@
// Don't adaptively route
// Makes sure ordering is reset
for (auto &link : m_links)
- link->m_order = static_cast<int>(link->m_link_id);
+ link->m_order = 0;
} else {
// Find how clogged each link is
for (auto &link : m_links) {
@@ -96,12 +98,7 @@
(out_queue_length << 8) | random_mt.random(0, 0xff);
}
}
-
- std::sort(m_links.begin(), m_links.end(),
- [](const std::unique_ptr<LinkInfo> &a,
- const std::unique_ptr<LinkInfo> &b) {
- return a->m_order < b->m_order;
- });
+ sortLinks();
}
findRoute(msg, out_links);
diff --git a/src/mem/ruby/network/simple/routing/WeightBased.hh
b/src/mem/ruby/network/simple/routing/WeightBased.hh
index e0a2472..a723e9b 100644
--- a/src/mem/ruby/network/simple/routing/WeightBased.hh
+++ b/src/mem/ruby/network/simple/routing/WeightBased.hh
@@ -60,7 +60,8 @@
void addOutPort(LinkID link_id,
const std::vector<MessageBuffer*>& m_out_buffer,
const NetDest& routing_table_entry,
- const PortDirection &direction) override;
+ const PortDirection &direction,
+ int link_weight) override;
void route(const Message &msg,
int vnet,
@@ -74,6 +75,7 @@
const NetDest m_routing_entry;
const std::vector<MessageBuffer*> m_out_buffers;
int m_order;
+ int m_weight;
};
std::vector<std::unique_ptr<LinkInfo>> m_links;
@@ -81,6 +83,16 @@
void findRoute(const Message &msg,
std::vector<RouteInfo> &out_links) const;
+ void sortLinks() {
+ std::sort(m_links.begin(), m_links.end(),
+ [](const auto &a, const auto &b) {
+ auto tup = [](const auto &li)
+ { return std::make_tuple(li->m_order,
+ li->m_weight,
+ li->m_link_id);};
+ return tup(a) < tup(b);
+ });
+ }
};
} // namespace ruby
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I86a4deb610a1b94abf745e9ef249961fb52e9800
Gerrit-Change-Number: 41860
Gerrit-PatchSet: 7
Gerrit-Owner: Tiago Muck <[email protected]>
Gerrit-Reviewer: Giacomo Travaglini <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Jason Lowe-Power <[email protected]>
Gerrit-Reviewer: Meatboy 106 <[email protected]>
Gerrit-Reviewer: Tiago Muck <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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