Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/56904 )
Change subject: arch-x86: Add the null selector check to m_read_descriptor.
......................................................................
arch-x86: Add the null selector check to m_read_descriptor.
Change-Id: Ifce7757e812265eec338b695551c19686254f65c
---
M
src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
M src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
M src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
M
src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
M src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
M src/arch/x86/microcode/macros/segmentation.ucode
M src/arch/x86/microcode/romutil.ucode
7 files changed, 13 insertions(+), 38 deletions(-)
diff --git
a/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
b/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
index f2b5a99..9640fcd 100644
---
a/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
+++
b/src/arch/x86/microcode/general_purpose/control_transfer/interrupts_and_exceptions.ucode
@@ -127,10 +127,7 @@
###
#CS = READ_DESCRIPTOR (temp_CS, iret_chk)
- andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- br "processCSDescriptor", flags=(CEZF,)
m_read_descriptor desc="t8", selector="t2"
-processCSDescriptor:
chks t0, t2, t8, NoCheck, dataSize=8
@@ -178,10 +175,7 @@
# POP.v temp_SS
ld t9, ss, [1, t0, rsp], "4 * env.dataSize", addressSize=ssz
# SS = READ_DESCRIPTOR (temp_SS, ss_chk)
- andi t0, t9, 0xFC, flags=(EZF,), dataSize=2
- br "processSSDescriptor", flags=(CEZF,)
m_read_descriptor desc="t7", selector="t9"
-processSSDescriptor:
chks t0, t9, t7, NoCheck, dataSize=8
# This actually updates state which is wrong. It should wait until we
know
diff --git
a/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
b/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
index 5c291f8..0542728 100644
--- a/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
+++ b/src/arch/x86/microcode/general_purpose/control_transfer/xreturn.ucode
@@ -139,10 +139,7 @@
# that doesn't happen yet.
# Do stuff if they're equal
- andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="t2"
-processDescriptor:
chks t0, t2, t3, IretCheck, dataSize=8
# There should be validity checks on the RIP checks here, but I'll do
# that later.
diff --git
a/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
b/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
index de4f060..0b35f08 100644
--- a/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
+++ b/src/arch/x86/microcode/general_purpose/data_transfer/move.ucode
@@ -265,10 +265,7 @@
def macroop MOV {
.args 'S', 'R'
- andi t0, regm, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="regm"
-processDescriptor:
chks t0, regm, t3, NoCheck, dataSize=8
wrdl sr, t3, regm
wrsel sr, regm
@@ -277,10 +274,7 @@
def macroop MOV {
.args 'S', 'M'
ld t1, seg, sib, disp, dataSize=2
- andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="t1"
-processDescriptor:
chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
@@ -290,10 +284,7 @@
.args 'S', 'P'
rdip t7
ld t1, seg, riprel, disp, dataSize=2
- andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="t1"
-processDescriptor:
chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
@@ -301,10 +292,7 @@
def macroop MOVSS {
.args 'S', 'R'
- andi t0, regm, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="regm"
-processDescriptor:
chks t0, regm, t3, SSCheck, dataSize=8
wrdl sr, t3, regm
wrsel sr, regm
@@ -313,10 +301,7 @@
def macroop MOVSS {
.args 'S', 'M'
ld t1, seg, sib, disp, dataSize=2
- andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="t1"
-processDescriptor:
chks t0, t1, t3, SSCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
@@ -326,10 +311,7 @@
.args 'S', 'P'
rdip t7
ld t1, seg, riprel, disp, dataSize=2
- andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
m_read_descriptor desc="t3", selector="t1"
-processDescriptor:
chks t0, t1, t3, SSCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
diff --git
a/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
b/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
index 643fb11..f010878 100644
---
a/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
+++
b/src/arch/x86/microcode/general_purpose/data_transfer/stack_operations.ucode
@@ -85,12 +85,8 @@
ld t1, ss, [1, t0, rsp], addressSize=ssz, dataSize=2
- andi t0, t1, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
-
m_read_descriptor desc="t3", selector="t1"
-processDescriptor:
chks t0, t1, t3, NoCheck, dataSize=8
wrdl sr, t3, t1
wrsel sr, t1
diff --git
a/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
b/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
index f0231b2..88c10b6 100644
--- a/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
+++ b/src/arch/x86/microcode/general_purpose/load_segment_registers.ucode
@@ -44,14 +44,9 @@
# Load the offset.
ld t1, seg, [1, t0, t1], 0
- # Figure out if this is a null selector.
- andi t0, t2, 0xFC, flags=(EZF,), dataSize=2
- br "processDescriptor", flags=(CEZF,)
-
m_read_descriptor desc="t4", selector="t2"
# Install the descriptor.
-processDescriptor:
chks t0, t2, t4, {"SSCheck" if seg == "ss" else "NoCheck"}, dataSize=8
wrdl {seg}, t4, t2
wrsel {seg}, t2
diff --git a/src/arch/x86/microcode/macros/segmentation.ucode
b/src/arch/x86/microcode/macros/segmentation.ucode
index d8c1b81..b956428 100644
--- a/src/arch/x86/microcode/macros/segmentation.ucode
+++ b/src/arch/x86/microcode/macros/segmentation.ucode
@@ -25,6 +25,10 @@
def macro m_read_descriptor desc, selector, label_prefix=rnd_str()
{
+ # Check for a null descriptor.
+ andi t0, {selector}, 0xFC, flags=(EZF,), dataSize=2
+ br "{label_prefix}_process_desc", flags=(CEZF,)
+
# Extract the index.
andi {desc}, {selector}, 0xF8, dataSize=8
diff --git a/src/arch/x86/microcode/romutil.ucode
b/src/arch/x86/microcode/romutil.ucode
index 27b1d36..13a9d2b 100644
--- a/src/arch/x86/microcode/romutil.ucode
+++ b/src/arch/x86/microcode/romutil.ucode
@@ -253,8 +253,6 @@
# Go get the stack segment descriptor
# Check for a null selector.
- andi t0, t8, 0xFC, flags=(EZF,), dataSize=8
- fault "std::make_shared<GeneralProtection>(0)", flags=(CEZF,)
m_read_descriptor desc="t12", selector="t8"
chks t0, t8, t12, SSCheck, dataSize=8
wrdl hs, t12, t8, dataSize=8
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/56904
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifce7757e812265eec338b695551c19686254f65c
Gerrit-Change-Number: 56904
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
