Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57051 )
Change subject: arch-x86: Fix some settings installed by the init interrupt.
......................................................................
arch-x86: Fix some settings installed by the init interrupt.
VMX requires that the present bit of the LDT and the TR are set, and
that the unusable bit of the TR is zero.
Change-Id: I4c4feba38d4fef11ad3b804d41dacb69cc3e6bd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57051
Maintainer: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Reviewed-by: Bobby Bruce <[email protected]>
Maintainer: Bobby Bruce <[email protected]>
---
M src/arch/x86/faults.cc
1 file changed, 20 insertions(+), 3 deletions(-)
Approvals:
Bobby Bruce: Looks good to me, approved; Looks good to me, approved
Gabe Black: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/x86/faults.cc b/src/arch/x86/faults.cc
index 09b4d99..209f3e8 100644
--- a/src/arch/x86/faults.cc
+++ b/src/arch/x86/faults.cc
@@ -256,7 +256,7 @@
SegAttr tslAttr = 0;
tslAttr.unusable = 1;
- tslAttr.present = 0;
+ tslAttr.present = 1;
tslAttr.type = 2; // LDT
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSL_BASE, 0);
@@ -264,8 +264,8 @@
tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
SegAttr trAttr = 0;
- trAttr.unusable = 1;
- trAttr.present = 0;
+ trAttr.unusable = 0;
+ trAttr.present = 1;
trAttr.type = 3; // Busy 16-bit TSS
tc->setMiscReg(MISCREG_TR, 0);
tc->setMiscReg(MISCREG_TR_BASE, 0);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I4c4feba38d4fef11ad3b804d41dacb69cc3e6bd5
Gerrit-Change-Number: 57051
Gerrit-PatchSet: 2
Gerrit-Owner: Gabe Black <[email protected]>
Gerrit-Reviewer: Bobby Bruce <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-MessageType: merged
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