ksco has submitted this change. ( https://gem5-review.googlesource.com/c/public/gem5/+/57069 )

Change subject: arch-riscv: Fix a typo in fsgnjn_s decoder
......................................................................

arch-riscv: Fix a typo in fsgnjn_s decoder

Negating the register value before unboxing to float32 will
generally result in a canonical 32-bit NaN (without the sign
bit set) so the result was incorrect in many cases.

Change-Id: I0c1bb3aadfca135ab0cc5ba1b58fc83d71fd300c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57069
Reviewed-by: Alex Richardson <[email protected]>
Reviewed-by: Gabe Black <[email protected]>
Maintainer: Gabe Black <[email protected]>
Reviewed-by: Luming Wang <[email protected]>
Tested-by: kokoro <[email protected]>
---
M src/arch/riscv/isa/decoder.isa
1 file changed, 29 insertions(+), 7 deletions(-)

Approvals:
  Gabe Black: Looks good to me, approved; Looks good to me, approved
  Luming Wang: Looks good to me, approved
  Alex Richardson: Looks good to me, but someone else must approve
  kokoro: Regressions pass




diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index e512e08..c109d96 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -1025,17 +1025,20 @@
                 }}, FloatDivOp);
                 0x10: decode ROUND_MODE {
                     0x0: fsgnj_s({{
- Fd_bits = boxF32(insertBits(unboxF32(Fs2_bits), 30, 0,
-                                                    unboxF32(Fs1_bits)));
+                        auto sign = bits(unboxF32(Fs2_bits), 31);
+                        Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
+                                                    sign));
                         }}, FloatMiscOp);
                     0x1: fsgnjn_s({{
- Fd_bits = boxF32(insertBits(unboxF32(~Fs2_bits), 30, 0,
-                                                    unboxF32(Fs1_bits)));
+                        auto sign = ~bits(unboxF32(Fs2_bits), 31);
+                        Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
+                                                    sign));
                         }}, FloatMiscOp);
                     0x2: fsgnjx_s({{
-                        Fd_bits = boxF32(insertBits(
- unboxF32(Fs1_bits) ^ unboxF32(Fs2_bits),
-                                    30, 0, unboxF32(Fs1_bits)));
+                        auto sign = bits(
+                            unboxF32(Fs1_bits) ^ unboxF32(Fs2_bits), 31);
+                        Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
+                                                    sign));
                         }}, FloatMiscOp);
                 }
                 0x11: decode ROUND_MODE {

--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I0c1bb3aadfca135ab0cc5ba1b58fc83d71fd300c
Gerrit-Change-Number: 57069
Gerrit-PatchSet: 3
Gerrit-Owner: ksco <[email protected]>
Gerrit-Reviewer: Alex Richardson <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Luming Wang <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-Reviewer: ksco <[email protected]>
Gerrit-MessageType: merged
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