Kyle Roarty has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57209 )
Change subject: arch-vega: Handle signed offsets in Global/Scratch
instructions
......................................................................
arch-vega: Handle signed offsets in Global/Scratch instructions
The offset field in Flat-style instructions is treated differently
based on if the instruction is Flat or Global/Scratch.
In Flat insts, the offset is treated as a 12-bit unsigned number.
In Global/Scratch insts, the offset is treated as a 13-bit signed number.
This patch updates the calcAddr function for Flat-style instructions
to properly sign-extend the offset on Global/Scratch instructions
Change-Id: I57f10258c23d900da9bf6ded6717c6e8abd177b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57209
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
Reviewed-by: Matthew Poremba <matthew.pore...@amd.com>
---
M src/arch/amdgpu/vega/insts/op_encodings.hh
1 file changed, 35 insertions(+), 3 deletions(-)
Approvals:
Matthew Poremba: Looks good to me, approved
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/amdgpu/vega/insts/op_encodings.hh
b/src/arch/amdgpu/vega/insts/op_encodings.hh
index 2642cd7..e9ce4cc 100644
--- a/src/arch/amdgpu/vega/insts/op_encodings.hh
+++ b/src/arch/amdgpu/vega/insts/op_encodings.hh
@@ -905,8 +905,16 @@
void
calcAddr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr,
- ScalarRegU32 saddr, ScalarRegU32 offset)
+ ScalarRegU32 saddr, ScalarRegI32 offset)
{
+ // Offset is a 13-bit field w/the following meanings:
+ // In Flat instructions, offset is a 12-bit unsigned number
+ // In Global/Scratch instructions, offset is a 13-bit signed
number
+ if (isFlat()) {
+ offset = offset & 0xfff;
+ } else {
+ offset = (ScalarRegI32)sext<13>(offset);
+ }
// If saddr = 0x7f there is no scalar reg to read and address
will
// be a 64-bit address. Otherwise, saddr is the reg index for a
// scalar reg used as the base address for a 32-bit address.
@@ -956,7 +964,7 @@
void
calcAddrSgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &vaddr,
- ConstScalarOperandU64 &saddr, ScalarRegU32 offset)
+ ConstScalarOperandU64 &saddr, ScalarRegI32 offset)
{
// Use SGPR pair as a base address and add VGPR-offset and
// instruction offset. The VGPR-offset is always 32-bits so we
@@ -971,7 +979,7 @@
void
calcAddrVgpr(GPUDynInstPtr gpuDynInst, ConstVecOperandU64 &addr,
- ScalarRegU32 offset)
+ ScalarRegI32 offset)
{
for (int lane = 0; lane < NumVecElemPerVecReg; ++lane) {
if (gpuDynInst->exec_mask[lane]) {
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I57f10258c23d900da9bf6ded6717c6e8abd177b7
Gerrit-Change-Number: 57209
Gerrit-PatchSet: 2
Gerrit-Owner: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Kyle Roarty <kyleroarty1...@gmail.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
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