Gabe Black has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/49719 )
(
56 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch: Introduce an intermediate RegOperand class in
operand_types.py.
......................................................................
arch: Introduce an intermediate RegOperand class in operand_types.py.
There are a number of operand types which are registers. Define a
RegOperand type which they can all inherit from to get register generic
functionality. This will also become a way to add generic register types
with malleable properties at the ISA level.
Change-Id: I01a1d5d133d8f64106d005a744631f64e6808e57
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49719
Reviewed-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/isa_parser/operand_types.py
1 file changed, 28 insertions(+), 25 deletions(-)
Approvals:
Giacomo Travaglini: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/isa_parser/operand_types.py
b/src/arch/isa_parser/operand_types.py
index e4d56c0..3a1e5a4 100755
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -170,13 +170,13 @@
# to avoid 'uninitialized variable' errors from the compiler.
return self.ctype + ' ' + self.base_name + ' = 0;\n';
-
-class IntRegOperand(Operand):
- reg_class = 'IntRegClass'
-
+class RegOperand(Operand):
def isReg(self):
return 1
+class IntRegOperand(RegOperand):
+ reg_class = 'IntRegClass'
+
def isIntReg(self):
return 1
@@ -243,12 +243,9 @@
return wb
-class FloatRegOperand(Operand):
+class FloatRegOperand(RegOperand):
reg_class = 'FloatRegClass'
- def isReg(self):
- return 1
-
def isFloatReg(self):
return 1
@@ -306,16 +303,13 @@
}''' % (self.ctype, self.base_name, wp)
return wb
-class VecRegOperand(Operand):
+class VecRegOperand(RegOperand):
reg_class = 'VecRegClass'
def __init__(self, parser, full_name, ext, is_src, is_dest):
- Operand.__init__(self, parser, full_name, ext, is_src, is_dest)
+ super().__init__(parser, full_name, ext, is_src, is_dest)
self.elemExt = None
- def isReg(self):
- return 1
-
def isVecReg(self):
return 1
@@ -453,12 +447,9 @@
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class VecElemOperand(Operand):
+class VecElemOperand(RegOperand):
reg_class = 'VecElemClass'
- def isReg(self):
- return 1
-
def isVecElem(self):
return 1
@@ -500,12 +491,9 @@
val = f'floatToBits64({val})'
return f'\n\txc->setRegOperand(this, {self.dest_reg_idx}, {val});'
-class VecPredRegOperand(Operand):
+class VecPredRegOperand(RegOperand):
reg_class = 'VecPredRegClass'
- def isReg(self):
- return 1
-
def isVecPredReg(self):
return 1
@@ -580,12 +568,9 @@
if self.is_dest:
self.op_rd = self.makeReadW(predWrite) + self.op_rd
-class CCRegOperand(Operand):
+class CCRegOperand(RegOperand):
reg_class = 'CCRegClass'
- def isReg(self):
- return 1
-
def isCCReg(self):
return 1
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/49719
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I01a1d5d133d8f64106d005a744631f64e6808e57
Gerrit-Change-Number: 49719
Gerrit-PatchSet: 58
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Gabe Black <gabe.bl...@gmail.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
