See <https://jenkins.gem5.org/job/nightly/167/display/redirect?page=changes>
Changes:
[gabe.black] arch-x86: Implement IntCSCheck for legacy mode.
[gabe.black] arch-x86: Use push_state in the microcode assembler.
[gabe.black] arch: Switch to a new state to process macrocoop headers.
[gabe.black] arch-x86: Remove __init__ from the X86MicrocodeRom class.
[gabe.black] arch,arch-x86: Consolidate the add_microop method.
[gabe.black] arch:arch-x86: Fix style of some classes in the ucode assembler.
[gabe.black] arch-x86: Add some missing checks to STI and CLI.
------------------------------------------
[...truncated 3.52 MB...]
[ SHCXX] RISCV/base/date.cc -> .os
[ SHCC] RISCV/ext/softfloat/f64_lt.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_lt_quiet.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_mulAdd.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_mul.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_rem.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_roundToInt.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_sqrt.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_sub.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_f128.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_f16.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_f32.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_i32.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_i32_r_minMag.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_i64.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_i64_r_minMag.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_ui32.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_ui32_r_minMag.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_ui64.c -> .os
[ SHCC] RISCV/ext/softfloat/f64_to_ui64_r_minMag.c -> .os
[ SHCC] RISCV/ext/softfloat/i32_to_f128.c -> .os
[ SHCC] RISCV/ext/softfloat/i32_to_f16.c -> .os
[ SHCC] RISCV/ext/softfloat/i32_to_f32.c -> .os
[ SHCC] RISCV/ext/softfloat/i32_to_f64.c -> .os
[ SHCC] RISCV/ext/softfloat/i64_to_f128.c -> .os
[ SHCC] RISCV/ext/softfloat/i64_to_f16.c -> .os
[ SHCC] RISCV/ext/softfloat/i64_to_f32.c -> .os
[ SHCC] RISCV/ext/softfloat/i64_to_f64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_add128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_add256M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addCarryM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addComplCarryM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addMagsF128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addMagsF16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addMagsF32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addMagsF64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_addM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_approxRecip_1Ks.c -> .os
[ SHCC] RISCV/ext/softfloat/s_approxRecip32_1.c -> .os
[ SHCC] RISCV/ext/softfloat/s_approxRecipSqrt_1Ks.c -> .os
[ SHCC] RISCV/ext/softfloat/s_approxRecipSqrt32_1.c -> .os
[ SHCC] RISCV/ext/softfloat/s_commonNaNToF128UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_commonNaNToF16UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_commonNaNToF32UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_commonNaNToF64UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_compare128M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_compare96M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_countLeadingZeros16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_countLeadingZeros32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_countLeadingZeros64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_countLeadingZeros8.c -> .os
[ SHCC] RISCV/ext/softfloat/s_eq128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_f128UIToCommonNaN.c -> .os
[ SHCC] RISCV/ext/softfloat/s_f16UIToCommonNaN.c -> .os
[ SHCC] RISCV/ext/softfloat/s_f32UIToCommonNaN.c -> .os
[ SHCC] RISCV/ext/softfloat/s_f64UIToCommonNaN.c -> .os
[ SHCC] RISCV/ext/softfloat/s_le128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_lt128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul128By32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul128MTo256M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul128To256M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul64ByShifted32To128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul64To128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mul64To128M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mulAddF128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mulAddF16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mulAddF32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_mulAddF64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_negXM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normRoundPackToF128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normRoundPackToF16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normRoundPackToF32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normRoundPackToF64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normSubnormalF128Sig.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normSubnormalF16Sig.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normSubnormalF32Sig.c -> .os
[ SHCC] RISCV/ext/softfloat/s_normSubnormalF64Sig.c -> .os
[ SHCC] RISCV/ext/softfloat/softfloat_raiseFlags.c -> .os
[ SHCC] RISCV/ext/softfloat/softfloat_state.c -> .os
[ SHCC] RISCV/ext/softfloat/s_propagateNaNF128UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_propagateNaNF16UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_propagateNaNF32UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_propagateNaNF64UI.c -> .os
[ SHCC] RISCV/ext/softfloat/s_remStepMBy32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundMToI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundMToUI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackMToI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackMToUI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToF128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToF16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToF32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToF64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToI32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToUI32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundPackToUI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundToI32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundToI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundToUI32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_roundToUI64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam128Extra.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam256M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shiftRightJam64Extra.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftLeft128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftLeft64To96M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRight128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightExtendM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os
[ SHCC] RISCV/ext/softfloat/s_shortShiftRightM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_sub128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_sub1XM.c -> .os
[ SHCC] RISCV/ext/softfloat/s_sub256M.c -> .os
[ SHCC] RISCV/ext/softfloat/s_subMagsF128.c -> .os
[ SHCC] RISCV/ext/softfloat/s_subMagsF16.c -> .os
[ SHCC] RISCV/ext/softfloat/s_subMagsF32.c -> .os
[ SHCC] RISCV/ext/softfloat/s_subMagsF64.c -> .os
[ SHCC] RISCV/ext/softfloat/s_subM.c -> .os
[ SHCC] RISCV/ext/softfloat/ui32_to_f128.c -> .os
[ SHCC] RISCV/ext/softfloat/ui32_to_f16.c -> .os
[ SHCC] RISCV/ext/softfloat/ui32_to_f32.c -> .os
[ SHCC] RISCV/ext/softfloat/ui32_to_f64.c -> .os
[ SHCC] RISCV/ext/softfloat/ui64_to_f128.c -> .os
[ SHCC] RISCV/ext/softfloat/ui64_to_f16.c -> .os
[ SHCC] RISCV/ext/softfloat/ui64_to_f32.c -> .os
[ SHCC] RISCV/ext/softfloat/ui64_to_f64.c -> .os
[ SHCC] RISCV/ext/libelf/elf.c -> .os
[ SHCC] RISCV/ext/libelf/elf_begin.c -> .os
[ SHCC] RISCV/ext/libelf/elf_cntl.c -> .os
[ AR] -> RISCV/ext/softfloat/libsoftfloat.a
[ SHCC] RISCV/ext/libelf/elf_data.c -> .os
[ SHCC] RISCV/ext/libelf/elf_end.c -> .os
[ RANLIB] -> RISCV/ext/softfloat/libsoftfloat.a
[ SHCC] RISCV/ext/libelf/elf_errmsg.c -> .os
[ SHCC] RISCV/ext/libelf/elf_errno.c -> .os
[ SHCC] RISCV/ext/libelf/elf_fill.c -> .os
[ SHCC] RISCV/ext/libelf/elf_flag.c -> .os
[ SHCC] RISCV/ext/libelf/elf_getarhdr.c -> .os
[ SHCC] RISCV/ext/libelf/elf_getarsym.c -> .os
[ SHCC] RISCV/ext/libelf/elf_getbase.c -> .os
[ SHCC] RISCV/ext/libelf/elf_getident.c -> .os
[ SHCC] RISCV/ext/libelf/elf_hash.c -> .os
[ SHCC] RISCV/ext/libelf/elf_kind.c -> .os
[ SHCC] RISCV/ext/libelf/elf_memory.c -> .os
[ SHCC] RISCV/ext/libelf/elf_next.c -> .os
[ SHCC] RISCV/ext/libelf/elf_open.c -> .os
[ SHCC] RISCV/ext/libelf/elf_phnum.c -> .os
[ SHCC] RISCV/ext/libelf/elf_rand.c -> .os
[ SHCC] RISCV/ext/libelf/elf_rawfile.c -> .os
[ SHCC] RISCV/ext/libelf/elf_scn.c -> .os
[ SHCC] RISCV/ext/libelf/elf_shnum.c -> .os
[ SHCC] RISCV/ext/libelf/elf_shstrndx.c -> .os
[ SHCC] RISCV/ext/libelf/elf_strptr.c -> .os
[ SHCC] RISCV/ext/libelf/elf_update.c -> .os
[ SHCC] RISCV/ext/libelf/elf_version.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_cap.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_checksum.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_dyn.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_ehdr.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_fsize.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_getclass.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_move.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_phdr.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_rel.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_rela.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_shdr.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_sym.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_syminfo.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_symshndx.c -> .os
[ SHCC] RISCV/ext/libelf/gelf_xlate.c -> .os
[ SHCC] RISCV/ext/libelf/libelf.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_align.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_allocate.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_ar.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_ar_util.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_checksum.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_data.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_ehdr.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_extended.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_memory.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_open.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_phdr.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_shdr.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_xlate.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_convert.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_fsize.c -> .os
[ SHCC] RISCV/ext/libelf/libelf_msize.c -> .os
[ AR] -> RISCV/ext/libelf/libelf.a
[ RANLIB] -> RISCV/ext/libelf/libelf.a
[ SHLINK] -> RISCV/libgem5_opt.so
scons: done building targets.
*** Summary of Warnings ***
Warning: Deprecated namespaces are not supported by this compiler.
Please make sure to check the mailing list for deprecation
announcements.
rm -f *.[do] libgem5.so
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst
-I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/
-I../../ext/pybind11/include/ -I../../build/softfloat/ -MMD -MP -c -o
sst_responder.o sst_responder.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst
-I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/
-I../../ext/pybind11/include/ -I../../build/softfloat/ -MMD -MP -c -o gem5.o
gem5.cc
g++ -std=c++17 -g -O3 -fPIC -DHAVE_CONFIG_H -I/sst/include -I/sst/include/sst
-I/usr/include/python3.8 -I/usr/include/python3.8 -I../../build/RISCV/
-I../../ext/pybind11/include/ -I../../build/softfloat/ -MMD -MP -c -o
sst_responder_subcomponent.o sst_responder_subcomponent.cc
g++ -MMD -MP -shared -fno-common -Wl,-undefined -Wl,dynamic_lookup
-L../../build/RISCV/ -Wl,-rpath ../../build/RISCV sst_responder.o gem5.o
sst_responder_subcomponent.o -o libgem5.so -lgem5_opt
gem5Component-gem5_node->Command string: [sst.x
../../configs/example/sst/riscv_fs.py --cpu-clock-rate 3GHz --memory-size 4GiB]
gem5Component-gem5_node-> Arg [00] = sst.x
gem5Component-gem5_node-> Arg [01] = ../../configs/example/sst/riscv_fs.py
gem5Component-gem5_node-> Arg [02] = --cpu-clock-rate
gem5Component-gem5_node-> Arg [03] = 3GHz
gem5Component-gem5_node-> Arg [04] = --memory-size
gem5Component-gem5_node-> Arg [05] = 4GiB
gem5Component-gem5_node-> init phase: 0
Global frequency set at 1000000000000 ticks per second
build/RISCV/sim/kernel_workload.cc:46: info: kernel located at:
/nobackup/jenkins/workspace/nightly/ext/sst/resources/riscv-boot-exit-nodisk
0: system.platform.rtc: Real-time clock set to Sun Jan 1 00:00:00 2012
build/RISCV/dev/serial/terminal.cc:170: warn: Sockets disabled, not accepting
terminal connections
build/RISCV/base/remote_gdb.cc:381: warn: Sockets disabled, not accepting gdb
connections
build/RISCV/arch/riscv/linux/fs_workload.cc:50: info: Loading DTB file:
m5out/device.dtb at address 0x87e00000
gem5.cc:287: info: Entering event queue @ 0. Starting simulation...
gem5Component-gem5_node-> init phase: 1
gem5Component-gem5_node-> init phase: 2
gem5Component-gem5_node-> init phase: 3
gem5Component-gem5_node-> init phase: 4
gem5Component-gem5_node-> init phase: 5
gem5Component-gem5_node->Component is being setup.
exiting: curTick()=1275684130575 cause=`m5_exit instruction encountered` code=0
gem5Component-gem5_node->Component is being finished.
Simulation is complete, simulated time: 1.27568 s
Archiving artifacts
Recording plot data
ERROR: Build step failed with exception
java.lang.NullPointerException
at hudson.plugins.plot.XMLSeries.addNodeToList(XMLSeries.java:276)
at hudson.plugins.plot.XMLSeries.loadSeries(XMLSeries.java:244)
at hudson.plugins.plot.Plot.addBuild(Plot.java:720)
at hudson.plugins.plot.Plot.addBuild(Plot.java:700)
at
hudson.plugins.plot.PlotPublisher.recordPlotData(PlotPublisher.java:151)
at hudson.plugins.plot.PlotPublisher.perform(PlotPublisher.java:142)
at hudson.tasks.BuildStepMonitor$3.perform(BuildStepMonitor.java:47)
at
hudson.model.AbstractBuild$AbstractBuildExecution.perform(AbstractBuild.java:814)
at
hudson.model.AbstractBuild$AbstractBuildExecution.performAllBuildSteps(AbstractBuild.java:763)
at hudson.model.Build$BuildExecution.post2(Build.java:179)
at
hudson.model.AbstractBuild$AbstractBuildExecution.post(AbstractBuild.java:707)
at hudson.model.Run.execute(Run.java:1921)
at hudson.model.FreeStyleBuild.run(FreeStyleBuild.java:44)
at hudson.model.ResourceController.execute(ResourceController.java:101)
at hudson.model.Executor.run(Executor.java:442)
Build step 'Plot build data' marked build as failure
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
