钟乘永 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58049 )
Change subject: arch-riscv: This commit fix the default privilege to M-mode
......................................................................
arch-riscv: This commit fix the default privilege to M-mode
As the spec(The RISC-V Instruction Set Manual Volume II: Privileged
Architecture,
chapter 3) says, "M-mode is used for low-level access to a hardware platform
and is the first mode entered at reset."
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1206
Change-Id: Ia4f33b2401a3d30211738d061848a15e5b12cf62
---
M src/arch/riscv/process.cc
1 file changed, 17 insertions(+), 2 deletions(-)
diff --git a/src/arch/riscv/process.cc b/src/arch/riscv/process.cc
index cbd13b0..361633d 100644
--- a/src/arch/riscv/process.cc
+++ b/src/arch/riscv/process.cc
@@ -102,7 +102,7 @@
argsInit<uint64_t>(PageBytes);
for (ContextID ctx: contextIds)
- system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+ system->threads[ctx]->setMiscRegNoEffect(MISCREG_PRV, PRV_M);
}
void
@@ -113,7 +113,7 @@
argsInit<uint32_t>(PageBytes);
for (ContextID ctx: contextIds) {
auto *tc = system->threads[ctx];
- tc->setMiscRegNoEffect(MISCREG_PRV, PRV_U);
+ tc->setMiscRegNoEffect(MISCREG_PRV, PRV_M);
PCState pc = tc->pcState().as<PCState>();
pc.rv32(true);
tc->pcState(pc);
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ia4f33b2401a3d30211738d061848a15e5b12cf62
Gerrit-Change-Number: 58049
Gerrit-PatchSet: 1
Gerrit-Owner: 钟乘永 <zhongc...@gmail.com>
Gerrit-MessageType: newchange
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