Matthew Poremba has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/57530 )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: dev-amdgpu: Always mark interrupts enabled
......................................................................
dev-amdgpu: Always mark interrupts enabled
The driver will check this bit is set after initializing IPs. Currently
the MMIO trace will cause this bit to be set at the correct time,
however this is not portable access different ROCm versions. Therefore
we modify the value to always set the bit indicating interrupts are
enabled.
Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57530
Reviewed-by: Matt Sinclair <mattdsincl...@gmail.com>
Maintainer: Matt Sinclair <mattdsincl...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/dev/amdgpu/amdgpu_device.cc
1 file changed, 33 insertions(+), 0 deletions(-)
Approvals:
Matt Sinclair: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/dev/amdgpu/amdgpu_device.cc
b/src/dev/amdgpu/amdgpu_device.cc
index 442e417..2badb6b 100644
--- a/src/dev/amdgpu/amdgpu_device.cc
+++ b/src/dev/amdgpu/amdgpu_device.cc
@@ -212,6 +212,20 @@
mmioReader.readFromTrace(pkt, MMIO_BAR, offset);
switch (aperture) {
+ case NBIO_BASE:
+ switch (aperture_offset) {
+ // This is a PCIe status register. At some point during driver
init
+ // the driver checks that interrupts are enabled. This is only
+ // checked once, so if the MMIO trace does not exactly line up
with
+ // what the driver is doing in gem5, this may still have the
first
+ // bit zero causing driver to fail. Therefore, we always set this
+ // bit to one as there is no harm to do so.
+ case 0x3c: // mmPCIE_DATA2 << 2
+ uint32_t value = pkt->getLE<uint32_t>() | 0x1;
+ DPRINTF(AMDGPUDevice, "Marking interrupts enabled: %#lx\n",
value);
+ pkt->setLE<uint32_t>(value);
+ break;
+ } break;
case GRBM_BASE:
gpuvm.readMMIO(pkt, aperture_offset >> GRBM_OFFSET_SHIFT);
break;
--
To view, visit https://gem5-review.googlesource.com/c/public/gem5/+/57530
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iae0baf1936720fbe9835ae4acadbf1b3bdc52896
Gerrit-Change-Number: 57530
Gerrit-PatchSet: 18
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: Matt Sinclair <mattdsincl...@gmail.com>
Gerrit-Reviewer: Matthew Poremba <matthew.pore...@amd.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- gem5-dev@gem5.org
To unsubscribe send an email to gem5-dev-le...@gem5.org
%(web_page_url)slistinfo%(cgiext)s/%(_internal_name)s
