钟乘永 has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58209 )
Change subject: arch-riscv: RISCV call/ret instructions aren't decoded
correctly
......................................................................
arch-riscv: RISCV call/ret instructions aren't decoded correctly
This change adds IsReturn flag for RISC-V ret instructions in decoder
, fix IsCall flag, and fixes target overwriting in buildRetPC.
Jira Issue: https://gem5.atlassian.net/browse/GEM5-1139
Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
---
M src/arch/riscv/insts/static_inst.hh
M src/arch/riscv/isa/decoder.isa
2 files changed, 87 insertions(+), 25 deletions(-)
diff --git a/src/arch/riscv/insts/static_inst.hh
b/src/arch/riscv/insts/static_inst.hh
index ef8032d..511c346 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -80,7 +80,7 @@
PCStateBase *ret_pc_ptr = call_pc.clone();
auto &ret_pc = ret_pc_ptr->as<PCState>();
ret_pc.advance();
- ret_pc.pc(cur_pc.as<PCState>().npc());
+ // ret_pc.pc(cur_pc.as<PCState>().npc());
return std::unique_ptr<PCStateBase>{ret_pc_ptr};
}
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index c109d96..abcb6f9 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -306,13 +306,22 @@
}
0x4: decode CFUNCT1 {
0x0: decode RC2 {
- 0x0: Jump::c_jr({{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
- NPC = Rc1;
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RC1 {
+ 0x1: Jump::c_jr_ret({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: Jump::c_jr({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0" ,machInst);
+ }
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl);
+ }
default: CROp::c_mv({{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
@@ -330,14 +339,24 @@
return
std::make_shared<BreakpointFault>(xc->pcState());
}}, IsSerializeAfter, IsNonSpeculative, No_OpClass);
default: decode RC2 {
- 0x0: Jump::c_jalr({{
- if (RC1 == 0) {
- return std::make_shared<IllegalInstFault>(
- "source reg x0", machInst);
- }
- ra = NPC;
- NPC = Rc1;
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RC1 {
+ 0x1: Jump::c_jalr_ret({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ ra = NPC;
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: Jump::c_jalr({{
+ if (RC1 == 0) {
+ return std::make_shared<IllegalInstFault>(
+ "source reg x0", machInst);
+ }
+ ra = NPC;
+ NPC = Rc1;
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ }
default: CompressedROp::c_add({{
Rc1_sd = Rc1_sd + Rc2_sd;
}});
@@ -1340,16 +1359,46 @@
}
0x19: decode FUNCT3 {
- 0x0: Jump::jalr({{
- Rd = NPC;
- NPC = (imm + Rs1) & (~0x1);
- }}, IsIndirectControl, IsUncondControl, IsCall);
+ 0x0: decode RS1 {
+ 0x1: decode IMM12 {
+ 0x0: Jump::ret({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsReturn);
+ default: decode RD {
+ 0x1: Jump::jalr_call_0({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ default: Jump::jalr_0({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl);
+ }
+ }
+ default: decode RD {
+ 0x1: Jump::jalr_call_1({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl, IsCall);
+ default: Jump::jalr_1({{
+ Rd = NPC;
+ NPC = (imm + Rs1) & (~0x1);
+ }}, IsIndirectControl, IsUncondControl);
+ }
+ }
}
- 0x1b: JOp::jal({{
- Rd = NPC;
- NPC = PC + imm;
- }}, IsDirectControl, IsUncondControl, IsCall);
+ 0x1b: decode RD{
+ 0x1: JOp::jal_call({{
+ Rd = NPC;
+ NPC = PC + imm;
+ }}, IsDirectControl, IsUncondControl, IsCall);
+ default: JOp::jal({{
+ Rd = NPC;
+ NPC = PC + imm;
+ }}, IsDirectControl, IsUncondControl);
+ }
0x1c: decode FUNCT3 {
format SystemOp {
@@ -1423,7 +1472,6 @@
} else {
STATUS status =
xc->readMiscReg(MISCREG_STATUS);
xc->setMiscReg(MISCREG_PRV, status.mpp);
- xc->setMiscReg(MISCREG_NMIE, 1);
status.mie = status.mpie;
status.mpie = 1;
status.mpp = PRV_U;
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9728757c9f3f81bd498a0ba04664a003dbded3bf
Gerrit-Change-Number: 58209
Gerrit-PatchSet: 1
Gerrit-Owner: 钟乘永 <[email protected]>
Gerrit-MessageType: newchange
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