Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58439 )
Change subject: configs,mem-ruby: Procotol-spec. names in CHI
......................................................................
configs,mem-ruby: Procotol-spec. names in CHI
Use the protocol-specific controller names in CHI.
**Important**: This could change some scripts. As long as people use
CHI_config (likely), this shouldn't be a problem, but if you have a
different version of CHI_config.py locally, you will need to make the
following updates:
`Cache_Controller` -> `CHI_Cache_Controller`
`Memory_Controller` -> `CHI_Memory_Controller`
Website updates coming soon!
Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M configs/ruby/CHI_config.py
M src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
M src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
3 files changed, 35 insertions(+), 13 deletions(-)
diff --git a/configs/ruby/CHI_config.py b/configs/ruby/CHI_config.py
index b596efa..8eb7aed 100644
--- a/configs/ruby/CHI_config.py
+++ b/configs/ruby/CHI_config.py
@@ -173,7 +173,7 @@
class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
ordered = True
-class CHI_Cache_Controller(Cache_Controller):
+class Base_CHI_Cache_Controller(CHI_Cache_Controller):
'''
Default parameters for a Cache controller
The Cache_Controller can also be used as a DMA requester or as
@@ -181,8 +181,8 @@
'''
def __init__(self, ruby_system):
- super(CHI_Cache_Controller, self).__init__(
- version = Versions.getVersion(Cache_Controller),
+ super(Base_CHI_Cache_Controller, self).__init__(
+ version = Versions.getVersion(CHI_Cache_Controller),
ruby_system = ruby_system,
mandatoryQueue = MessageBuffer(),
prefetchQueue = MessageBuffer(),
@@ -200,7 +200,7 @@
# timeouts on unique lines when a store conditional fails
self.sc_lock_enabled = False
-class CHI_L1Controller(CHI_Cache_Controller):
+class CHI_L1Controller(Base_CHI_Cache_Controller):
'''
Default parameters for a L1 Cache controller
'''
@@ -232,7 +232,7 @@
self.number_of_snoop_TBEs = 4
self.unify_repl_TBEs = False
-class CHI_L2Controller(CHI_Cache_Controller):
+class CHI_L2Controller(Base_CHI_Cache_Controller):
'''
Default parameters for a L2 Cache controller
'''
@@ -264,7 +264,7 @@
self.number_of_snoop_TBEs = 16
self.unify_repl_TBEs = False
-class CHI_HNFController(CHI_Cache_Controller):
+class CHI_HNFController(Base_CHI_Cache_Controller):
'''
Default parameters for a coherent home node (HNF) cache controller
'''
@@ -297,7 +297,7 @@
self.number_of_snoop_TBEs = 1 # should not receive any snoop
self.unify_repl_TBEs = False
-class CHI_DMAController(CHI_Cache_Controller):
+class CHI_DMAController(Base_CHI_Cache_Controller):
'''
Default parameters for a DMA controller
'''
@@ -545,8 +545,8 @@
def __init__(self, ruby_system, parent):
super(CHI_SNF_Base, self).__init__(ruby_system)
- self._cntrl = Memory_Controller(
- version = Versions.getVersion(Memory_Controller),
+ self._cntrl = CHI_Memory_Controller(
+ version =
Versions.getVersion(CHI_Memory_Controller),
ruby_system = ruby_system,
triggerQueue = TriggerMessageBuffer(),
responseFromMemory = MessageBuffer(),
diff --git
a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
index e8797b6..285cd68 100644
--- a/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
+++ b/src/python/gem5/components/cachehierarchies/chi/nodes/abstract_node.py
@@ -29,7 +29,7 @@
from gem5.components.processors.cpu_types import CPUTypes
from gem5.components.processors.abstract_core import AbstractCore
-from m5.objects import Cache_Controller, MessageBuffer, RubyNetwork
+from m5.objects import CHI_Cache_Controller, MessageBuffer, RubyNetwork
import math
@@ -45,7 +45,7 @@
class OrderedTriggerMessageBuffer(TriggerMessageBuffer):
ordered = True
-class AbstractNode(Cache_Controller):
+class AbstractNode(CHI_Cache_Controller):
"""A node is the abstract unit for caches in the CHI protocol.
You can extend the AbstractNode to create caches (private or shared)
and
diff --git
a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
index cf7d660..00fc225 100644
---
a/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
+++
b/src/python/gem5/components/cachehierarchies/chi/nodes/memory_controller.py
@@ -28,7 +28,7 @@
from m5.objects import (
AddrRange,
- Memory_Controller,
+ CHI_Memory_Controller,
MessageBuffer,
Port,
RubyNetwork,
@@ -36,7 +36,7 @@
from .abstract_node import TriggerMessageBuffer
-class MemoryController(Memory_Controller):
+class MemoryController(CHI_Memory_Controller):
"""A controller that connects to memory
"""
_version = 0
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I7afdcede884ac5f9a9a76cc3d3dd35941e4e2faa
Gerrit-Change-Number: 58439
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-MessageType: newchange
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