Jason Lowe-Power has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/58440 )
Change subject: stdlib,mem-ruby: Use protocol-spec. names
......................................................................
stdlib,mem-ruby: Use protocol-spec. names
Update the standard library Ruby protocols to use the protocol-specific
class names instead of the deprecated general names.
Unfortunately, some code became duplicated between similar controllers.
I tried multiple inheritance, but it didn't work out for me. I think the
correct solution is to move some of the shared code down into the
generated python. That's out of the scope for these changes.
Change-Id: I3444bee3c2917dcbe92b600b85e60244129aad35
Signed-off-by: Jason Lowe-Power <ja...@lowepower.com>
---
M src/python/SConscript
D
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
D
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
D
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
D
src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
M
src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py
12 files changed, 160 insertions(+), 280 deletions(-)
diff --git a/src/python/SConscript b/src/python/SConscript
index bb069f5..30c0ec5 100644
--- a/src/python/SConscript
+++ b/src/python/SConscript
@@ -106,14 +106,6 @@
'gem5/components/cachehierarchies/ruby/mi_example_cache_hierarchy.py')
PySource('gem5.components.cachehierarchies.ruby.caches',
'gem5/components/cachehierarchies/ruby/caches/__init__.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
- 'gem5/components/cachehierarchies/ruby/caches/abstract_directory.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
- 'gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
- 'gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py')
-PySource('gem5.components.cachehierarchies.ruby.caches',
- 'gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py')
PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
'gem5/components/cachehierarchies/ruby/caches/mesi_two_level/__init__.py')
PySource('gem5.components.cachehierarchies.ruby.caches.mesi_two_level',
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
deleted file mode 100644
index e39a38c..0000000
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_directory.py
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-
-from m5.objects import Directory_Controller
-
-
-class AbstractDirectory(Directory_Controller):
-
- _version = 0
-
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, network, cache_line_size):
- """ """
- super().__init__()
- self.version = self.versionCount()
- self._cache_line_size = cache_line_size
- self.connectQueues(network)
-
- @abstractmethod
- def connectQueues(self, network):
- """Connect all of the queues for this controller."""
- raise NotImplementedError
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
deleted file mode 100644
index 8d36736..0000000
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_dma_controller.py
+++ /dev/null
@@ -1,50 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-
-from m5.objects import DMA_Controller
-
-
-class AbstractDMAController(DMA_Controller):
-
- _version = 0
-
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, network, cache_line_size):
- super().__init__()
- self.version = self.versionCount()
- self._cache_line_size = cache_line_size
- self.connectQueues(network)
-
- @abstractmethod
- def connectQueues(self, network):
- """Connect all of the queues for this controller."""
- raise NotImplementedError
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
deleted file mode 100644
index 7f014dc..0000000
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l1_cache.py
+++ /dev/null
@@ -1,76 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-from .....isas import ISA
-from ....processors.cpu_types import CPUTypes
-from ....processors.abstract_core import AbstractCore
-
-from m5.objects import L1Cache_Controller
-
-import math
-
-
-class AbstractL1Cache(L1Cache_Controller):
-
- _version = 0
-
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- # TODO: I don't love that we have to pass in the cache line size.
- # However, we need some way to set the index bits
- def __init__(self, network, cache_line_size):
- """ """
- super().__init__()
-
- self.version = self.versionCount()
- self._cache_line_size = cache_line_size
- self.connectQueues(network)
-
- def getBlockSizeBits(self):
- bits = int(math.log(self._cache_line_size, 2))
- if 2 ** bits != self._cache_line_size.value:
- raise Exception("Cache line size not a power of 2!")
- return bits
-
- def sendEvicts(self, core: AbstractCore, target_isa: ISA):
- """True if the CPU model or ISA requires sending evictions from
caches
- to the CPU. Two scenarios warrant forwarding evictions to the CPU:
- 1. The O3 model must keep the LSQ coherent with the caches
- 2. The x86 mwait instruction is built on top of coherence
- 3. The local exclusive monitor in ARM systems
- """
- if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86,
ISA.ARM):
- return True
- return False
-
- @abstractmethod
- def connectQueues(self, network):
- """Connect all of the queues for this controller."""
- raise NotImplementedError
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
deleted file mode 100644
index 88b4122..0000000
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/abstract_l2_cache.py
+++ /dev/null
@@ -1,51 +0,0 @@
-# Copyright (c) 2021 The Regents of the University of California
-# All Rights Reserved.
-#
-# Redistribution and use in source and binary forms, with or without
-# modification, are permitted provided that the following conditions are
-# met: redistributions of source code must retain the above copyright
-# notice, this list of conditions and the following disclaimer;
-# redistributions in binary form must reproduce the above copyright
-# notice, this list of conditions and the following disclaimer in the
-# documentation and/or other materials provided with the distribution;
-# neither the name of the copyright holders nor the names of its
-# contributors may be used to endorse or promote products derived from
-# this software without specific prior written permission.
-#
-# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
-# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
-# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
-# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-from abc import abstractmethod
-
-from m5.objects import L2Cache_Controller
-
-
-class AbstractL2Cache(L2Cache_Controller):
-
- _version = 0
-
- @classmethod
- def versionCount(cls):
- cls._version += 1 # Use count for this particular type
- return cls._version - 1
-
- def __init__(self, network, cache_line_size):
- super().__init__()
-
- self.version = self.versionCount()
- self._cache_line_size = cache_line_size
- self.connectQueues(network)
-
- @abstractmethod
- def connectQueues(self, network):
- """Connect all of the queues for this controller."""
- raise NotImplementedError
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
index 990b0bf..62b4745 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/directory.py
@@ -24,25 +24,34 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ......utils.override import overrides
-from ..abstract_directory import AbstractDirectory
from m5.objects import (
MessageBuffer,
+ MESI_Two_Level_Directory_Controller,
RubyDirectoryMemory,
)
-class Directory(AbstractDirectory):
- def __init__(self, network, cache_line_size, mem_range, port):
+class Directory( MESI_Two_Level_Directory_Controller):
- super().__init__(network, cache_line_size)
+ _version = 0
+
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, network, cache_line_size, mem_range, port):
+ super().__init__()
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
+
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.
self.memory_out_port = port
- @overrides(AbstractDirectory)
def connectQueues(self, network):
self.requestToDir = MessageBuffer()
self.requestToDir.in_port = network.out_port
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
index ab76d4c..2b13e9f 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/dma_controller.py
@@ -24,17 +24,23 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ......utils.override import overrides
-from ..abstract_dma_controller import AbstractDMAController
-
-from m5.objects import MessageBuffer
+from m5.objects import MESI_Two_Level_DMA_Controller, MessageBuffer
-class DMAController(AbstractDMAController):
+class DMAController(MESI_Two_Level_DMA_Controller):
+
+ _version = 0
+
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
def __init__(self, network, cache_line_size):
- super().__init__(network, cache_line_size)
+ super().__init__()
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
- @overrides(AbstractDMAController)
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.responseFromDir = MessageBuffer(ordered=True)
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
index 7f6269d..f7580b7 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l1_cache.py
@@ -25,11 +25,11 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from .....processors.abstract_core import AbstractCore
+from .....processors.cpu_types import CPUTypes
from ......isas import ISA
-from ..abstract_l1_cache import AbstractL1Cache
-from ......utils.override import *
from m5.objects import (
+ MESI_Two_Level_L1Cache_Controller,
MessageBuffer,
RubyPrefetcher,
RubyCache,
@@ -39,7 +39,15 @@
import math
-class L1Cache(AbstractL1Cache):
+class L1Cache(MESI_Two_Level_L1Cache_Controller):
+
+ _version = 0
+
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
def __init__(
self,
l1i_size,
@@ -56,7 +64,11 @@
"""Creating L1 cache controller. Consist of both instruction
and data cache.
"""
- super().__init__(network, cache_line_size)
+ super().__init__()
+
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
# This is the cache memory object that stores the cache data and
tags
self.L1Icache = RubyCache(
@@ -78,7 +90,23 @@
self.transitions_per_cycle = 4
self.enable_prefetch = False
- @overrides(AbstractL1Cache)
+ def getBlockSizeBits(self):
+ bits = int(math.log(self._cache_line_size, 2))
+ if 2 ** bits != self._cache_line_size.value:
+ raise Exception("Cache line size not a power of 2!")
+ return bits
+
+ def sendEvicts(self, core: AbstractCore, target_isa: ISA):
+ """True if the CPU model or ISA requires sending evictions from
caches
+ to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+ 1. The O3 model must keep the LSQ coherent with the caches
+ 2. The x86 mwait instruction is built on top of coherence
+ 3. The local exclusive monitor in ARM systems
+ """
+ if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86,
ISA.ARM):
+ return True
+ return False
+
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.requestFromL1Cache = MessageBuffer()
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
index 56cb5b2..b490e6d 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mesi_two_level/l2_cache.py
@@ -24,19 +24,32 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ..abstract_l2_cache import AbstractL2Cache
-from ......utils.override import *
-
-from m5.objects import MessageBuffer, RubyCache
+from m5.objects import (
+ MessageBuffer,
+ MESI_Two_Level_L2Cache_Controller,
+ RubyCache,
+)
import math
-class L2Cache(AbstractL2Cache):
+class L2Cache(MESI_Two_Level_L2Cache_Controller):
+
+ _version = 0
+
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
def __init__(
self, l2_size, l2_assoc, network, num_l2Caches, cache_line_size
):
- super().__init__(network, cache_line_size)
+ super().__init__()
+
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
# This is the cache memory object that stores the cache data and
tags
self.L2cache = RubyCache(
@@ -52,7 +65,6 @@
bits = int(math.log(self._cache_line_size, 2)) + l2_bits
return bits
- @overrides(AbstractL2Cache)
def connectQueues(self, network):
self.DirRequestFromL2Cache = MessageBuffer()
self.DirRequestFromL2Cache.out_port = network.in_port
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
index 23216ec..968f477 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/directory.py
@@ -24,30 +24,36 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ..abstract_directory import AbstractDirectory
-from ......utils.override import overrides
-
-
from m5.objects import (
MessageBuffer,
+ MI_example_Directory_Controller,
RubyDirectoryMemory,
)
-class Directory(AbstractDirectory):
+class Directory(MI_example_Directory_Controller):
"""
The directory controller for the MI_Example cache hierarchy.
"""
- def __init__(self, network, cache_line_size, mem_range, port):
+ _version = 0
- super().__init__(network, cache_line_size)
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, network, cache_line_size, mem_range, port):
+ super().__init__()
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
+
self.addr_ranges = [mem_range]
self.directory = RubyDirectoryMemory()
# Connect this directory to the memory side.
self.memory_out_port = port
- @overrides(AbstractDirectory)
def connectQueues(self, network):
self.requestToDir = MessageBuffer(ordered=True)
self.requestToDir.in_port = network.out_port
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
index fb6895f..c1fbaec 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/dma_controller.py
@@ -27,19 +27,27 @@
from ..abstract_dma_controller import AbstractDMAController
from ......utils.override import overrides
-from m5.objects import MessageBuffer
+from m5.objects import MessageBuffer, MI_example_DMA_Controller
-class DMAController(AbstractDMAController):
+class DMAController(MI_example_DMA_Controller):
"""
A DMA Controller for use in the MI_Example cache hierarchy setup.
"""
- class DMAController(AbstractDMAController):
- def __init__(self, network, cache_line_size):
- super().__init__(network, cache_line_size)
+ _version = 0
- @overrides(AbstractDMAController)
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
+ def __init__(self, network, cache_line_size):
+ super().__init__()
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
+
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.requestToDir = MessageBuffer()
diff --git
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py
index 62adfb7..eeac328 100644
---
a/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py
+++
b/src/python/gem5/components/cachehierarchies/ruby/caches/mi_example/l1_cache.py
@@ -24,19 +24,29 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-from ......utils.override import overrides
+import math
+
+from .....processors.cpu_types import CPUTypes
from .....processors.abstract_core import AbstractCore
from ......isas import ISA
-from ..abstract_l1_cache import AbstractL1Cache
from m5.objects import (
MessageBuffer,
+ MI_example_L1Cache_Controller,
RubyCache,
ClockDomain,
)
-class L1Cache(AbstractL1Cache):
+class L1Cache(MI_example_L1Cache_Controller):
+
+ _version = 0
+
+ @classmethod
+ def versionCount(cls):
+ cls._version += 1 # Use count for this particular type
+ return cls._version - 1
+
def __init__(
self,
size: str,
@@ -47,7 +57,10 @@
target_isa: ISA,
clk_domain: ClockDomain,
):
- super().__init__(network, cache_line_size)
+ super().__init__()
+ self.version = self.versionCount()
+ self._cache_line_size = cache_line_size
+ self.connectQueues(network)
self.cacheMemory = RubyCache(
size=size, assoc=assoc, start_index_bit=self.getBlockSizeBits()
@@ -56,7 +69,23 @@
self.clk_domain = clk_domain
self.send_evictions = self.sendEvicts(core=core,
target_isa=target_isa)
- @overrides(AbstractL1Cache)
+ def getBlockSizeBits(self):
+ bits = int(math.log(self._cache_line_size, 2))
+ if 2 ** bits != self._cache_line_size.value:
+ raise Exception("Cache line size not a power of 2!")
+ return bits
+
+ def sendEvicts(self, core: AbstractCore, target_isa: ISA):
+ """True if the CPU model or ISA requires sending evictions from
caches
+ to the CPU. Two scenarios warrant forwarding evictions to the CPU:
+ 1. The O3 model must keep the LSQ coherent with the caches
+ 2. The x86 mwait instruction is built on top of coherence
+ 3. The local exclusive monitor in ARM systems
+ """
+ if core.get_type() is CPUTypes.O3 or target_isa in (ISA.X86,
ISA.ARM):
+ return True
+ return False
+
def connectQueues(self, network):
self.mandatoryQueue = MessageBuffer()
self.requestFromCache = MessageBuffer(ordered=True)
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3444bee3c2917dcbe92b600b85e60244129aad35
Gerrit-Change-Number: 58440
Gerrit-PatchSet: 1
Gerrit-Owner: Jason Lowe-Power <power...@gmail.com>
Gerrit-MessageType: newchange
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