[gem5-dev] [S] Change in gem5/gem5[develop]: fastmodel: Add CortexA76 artifact reset port

[Yu-hsin Wang (Gerrit) via gem5-dev]

Yu-hsin Wang has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/58814 )

Change subject: fastmodel: Add CortexA76 artifact reset port
......................................................................

fastmodel: Add CortexA76 artifact reset port

The artifact reset is an aggregated logic to reset the whole model. The
port helps us to simulate the reboot process.

Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
---
M src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
M src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
M src/arch/arm/fastmodel/CortexA76/evs.cc
M src/arch/arm/fastmodel/CortexA76/evs.hh
4 files changed, 40 insertions(+), 2 deletions(-)



diff --git a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py  
b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
index 9a56f29..420b499 100644
--- a/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
+++ b/src/arch/arm/fastmodel/CortexA76/FastModelCortexA76.py
@@ -31,6 +31,7 @@
 from m5.objects.ArmISA import ArmISA
 from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
 from m5.objects.FastModelGIC import Gicv3CommsTargetSocket
+from m5.objects.FastModelResetPort import FastModelResetResponsePort
 from m5.objects.IntPin import IntSinkPin
 from m5.objects.Gic import ArmPPI
 from m5.objects.Iris import IrisBaseCPU
@@ -172,6 +173,8 @@
             'all resettable registers in DynamIQ.')
     dbg_reset = IntSinkPin('Initialize the shared debug APB, Cross  
Trigger ' \
             'Interface (CTI), and Cross Trigger Matrix (CTM) logic.')
+    artifact_reset = FastModelResetResponsePort(
+        'An artifact reset port to reset the whole cluster.')

     # These parameters are described in "Fast Models Reference Manual"  
section
     # 3.4.19, "ARMCortexA7x1CT".
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc  
b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index e67a0f6..24f873b 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -104,7 +104,8 @@
 Port &
 CortexA76::getPort(const std::string &if_name, PortID idx)
 {
-    if (if_name == "redistributor" || if_name == "core_reset")
+    if (if_name == "redistributor" || if_name == "core_reset" ||
+        if_name == "poweron_reset")
         return cluster->getEvs()->gem5_getPort(if_name, num);
     else
         return Base::getPort(if_name, idx);
@@ -200,7 +201,7 @@
 CortexA76Cluster::getPort(const std::string &if_name, PortID idx)
 {
     if (if_name == "amba" || if_name == "top_reset" ||
-        if_name == "dbg_reset") {
+        if_name == "dbg_reset" || if_name == "artifact_reset") {
         return evs->gem5_getPort(if_name, idx);
     } else {
         return SimObject::getPort(if_name, idx);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc  
b/src/arch/arm/fastmodel/CortexA76/evs.cc
index d54ad78..76b2840 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -71,12 +71,27 @@
 }

 template <class Types>
+void
+ScxEvsCortexA76<Types>::requestReset()
+{
+    // Reset all cores.
+    for (auto &poweron_reset : this->poweron_reset) {
+        poweron_reset->signal_out.set_state(0, true);
+    }
+    // Reset DSU.
+    this->top_reset.signal_out.set_state(0, true);
+    // Reset debug APB.
+    this->dbg_reset.signal_out.set_state(0, true);
+}
+
+template <class Types>
 ScxEvsCortexA76<Types>::ScxEvsCortexA76(
         const sc_core::sc_module_name &mod_name, const Params &p) :
     Base(mod_name),
     amba(Base::amba, p.name + ".amba", -1),
     top_reset(p.name + ".top_reset", 0),
     dbg_reset(p.name + ".dbg_reset", 0),
+    artifact_reset(p.name + ".artifact_reset", -1, this),
     params(p)
 {
     for (int i = 0; i < CoreCount; i++) {
@@ -178,6 +193,8 @@
         return top_reset;
     else if (if_name == "dbg_reset")
         return dbg_reset;
+    else if (if_name == "artifact_reset")
+        return artifact_reset;
     else
         return Base::gem5_getPort(if_name, idx);
 }
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh  
b/src/arch/arm/fastmodel/CortexA76/evs.hh
index e1b6aed..28a473d 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -31,6 +31,7 @@
 #include <memory>

 #include "arch/arm/fastmodel/amba_ports.hh"
+#include "arch/arm/fastmodel/common/reset_port.hh"
 #include "arch/arm/fastmodel/common/signal_receiver.hh"
 #include "arch/arm/fastmodel/common/signal_sender.hh"
 #include "arch/arm/fastmodel/iris/cpu.hh"
@@ -98,6 +99,8 @@

     SignalSender dbg_reset;

+    ResetResponsePort<ScxEvsCortexA76> artifact_reset;
+
     CortexA76Cluster *gem5CpuCluster;

     const Params &params;
@@ -126,6 +129,8 @@
     void setCluster(SimObject *cluster) override;

     void setResetAddr(int core, Addr addr, bool secure) override;
+
+    void requestReset();
 };

 struct ScxEvsCortexA76x1Types

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I9aacc398b299e26e4675f7229db1afc8f6c8a34f
Gerrit-Change-Number: 58814
Gerrit-PatchSet: 1
Gerrit-Owner: Yu-hsin Wang <yuhsi...@google.com>
Gerrit-MessageType: newchange
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