Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/64912?usp=email )
Change subject: arch-arm: Setup ThreadContext in GICv3 cpu interface
......................................................................
arch-arm: Setup ThreadContext in GICv3 cpu interface
Change-Id: If019b4b114031f880dff43e05658a162c201ea6a
Signed-off-by: Giacomo Travaglini <[email protected]>
---
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc
b/src/dev/arm/gic_v3_cpu_interface.cc
index b089ba0..40ca1cc 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -81,8 +81,9 @@
}
void
-Gicv3CPUInterface::setThreadContext(ThreadContext *tc)
+Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
{
+ tc = _tc;
maintenanceInterrupt = gic->params().maint_int->get(tc);
fatal_if(maintenanceInterrupt->num() >=
redistributor->irqPending.size(),
"Invalid maintenance interrupt number\n");
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh
b/src/dev/arm/gic_v3_cpu_interface.hh
index dfc17af..e860373 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -71,6 +71,7 @@
uint32_t cpuId;
ArmInterruptPin *maintenanceInterrupt;
+ ThreadContext *tc;
BitUnion64(ICC_CTLR_EL1)
Bitfield<63, 20> res0_3;
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/64912?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: If019b4b114031f880dff43e05658a162c201ea6a
Gerrit-Change-Number: 64912
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <[email protected]>
Gerrit-MessageType: newchange
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
