See <https://jenkins.gem5.org/job/weekly/85/display/redirect?page=changes>
Changes: [sascha.bischoff] arch-arm: Set ZCR_ELx before updating vector length in decoder [ztqiu] stdlib: add SimPoint checkpoint generator ------------------------------------------ [...truncated 551.19 KB...] [ SHCC] RISCV/ext/softfloat/f32_classify.c -> .os [ SHCC] RISCV/ext/softfloat/f32_div.c -> .os [ SHCC] RISCV/ext/softfloat/f32_eq.c -> .os [ SHCC] RISCV/ext/softfloat/f32_eq_signaling.c -> .os [ SHCC] RISCV/ext/softfloat/f32_isSignalingNaN.c -> .os [ SHCC] RISCV/ext/softfloat/f32_le.c -> .os [ SHCC] RISCV/ext/softfloat/f32_le_quiet.c -> .os [ SHCC] RISCV/ext/softfloat/f32_lt.c -> .os [ SHCC] RISCV/ext/softfloat/f32_lt_quiet.c -> .os [ SHCC] RISCV/ext/softfloat/f32_mulAdd.c -> .os [ SHCC] RISCV/ext/softfloat/f32_mul.c -> .os [ SHCC] RISCV/ext/softfloat/f32_rem.c -> .os [ SHCC] RISCV/ext/softfloat/f32_roundToInt.c -> .os [ SHCC] RISCV/ext/softfloat/f32_sqrt.c -> .os [ CXX] RISCV/base/date.cc -> .o [ SHCC] RISCV/ext/softfloat/f32_sub.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_f64.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_i32.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_i32_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_i64.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_i64_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_ui32.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_ui32_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_ui64.c -> .os [ SHCC] RISCV/ext/softfloat/f32_to_ui64_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f64_add.c -> .os [ SHCC] RISCV/ext/softfloat/f64_classify.c -> .os [ SHCC] RISCV/ext/softfloat/f64_div.c -> .os [ SHCC] RISCV/ext/softfloat/f64_eq.c -> .os [ SHCC] RISCV/ext/softfloat/f64_eq_signaling.c -> .os [ SHCC] RISCV/ext/softfloat/f64_isSignalingNaN.c -> .os [ SHCC] RISCV/ext/softfloat/f64_le.c -> .os [ SHCC] RISCV/ext/softfloat/f64_le_quiet.c -> .os [ SHCC] RISCV/ext/softfloat/f64_lt.c -> .os [ SHCC] RISCV/ext/softfloat/f64_lt_quiet.c -> .os [ SHCC] RISCV/ext/softfloat/f64_mulAdd.c -> .os [ SHCC] RISCV/ext/softfloat/f64_mul.c -> .os [ SHCC] RISCV/ext/softfloat/f64_rem.c -> .os [ SHCC] RISCV/ext/softfloat/f64_roundToInt.c -> .os [ SHCC] RISCV/ext/softfloat/f64_sqrt.c -> .os [ SHCC] RISCV/ext/softfloat/f64_sub.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_f32.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_i32.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_i32_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_i64.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_i64_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_ui32.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_ui32_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_ui64.c -> .os [ SHCC] RISCV/ext/softfloat/f64_to_ui64_r_minMag.c -> .os [ SHCC] RISCV/ext/softfloat/i32_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/i32_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/i32_to_f32.c -> .os [ SHCC] RISCV/ext/softfloat/i32_to_f64.c -> .os [ SHCC] RISCV/ext/softfloat/i64_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/i64_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/i64_to_f32.c -> .os [ SHCC] RISCV/ext/softfloat/i64_to_f64.c -> .os [ SHCC] RISCV/ext/softfloat/s_add128.c -> .os [ SHCC] RISCV/ext/softfloat/s_add256M.c -> .os [ SHCC] RISCV/ext/softfloat/s_addCarryM.c -> .os [ SHCC] RISCV/ext/softfloat/s_addComplCarryM.c -> .os [ SHCC] RISCV/ext/softfloat/s_addMagsF128.c -> .os [ SHCC] RISCV/ext/softfloat/s_addMagsF16.c -> .os [ SHCC] RISCV/ext/softfloat/s_addMagsF32.c -> .os [ SHCC] RISCV/ext/softfloat/s_addMagsF64.c -> .os [ SHCC] RISCV/ext/softfloat/s_addM.c -> .os [ SHCC] RISCV/ext/softfloat/s_approxRecip_1Ks.c -> .os [ SHCC] RISCV/ext/softfloat/s_approxRecip32_1.c -> .os [ SHCC] RISCV/ext/softfloat/s_approxRecipSqrt_1Ks.c -> .os [ SHCC] RISCV/ext/softfloat/s_approxRecipSqrt32_1.c -> .os [ SHCC] RISCV/ext/softfloat/s_commonNaNToF128UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_commonNaNToF16UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_commonNaNToF32UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_commonNaNToF64UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_compare128M.c -> .os [ SHCC] RISCV/ext/softfloat/s_compare96M.c -> .os [ SHCC] RISCV/ext/softfloat/s_countLeadingZeros16.c -> .os [ SHCC] RISCV/ext/softfloat/s_countLeadingZeros32.c -> .os [ SHCC] RISCV/ext/softfloat/s_countLeadingZeros64.c -> .os [ SHCC] RISCV/ext/softfloat/s_countLeadingZeros8.c -> .os [ SHCC] RISCV/ext/softfloat/s_eq128.c -> .os [ SHCC] RISCV/ext/softfloat/s_f128UIToCommonNaN.c -> .os [ SHCC] RISCV/ext/softfloat/s_f16UIToCommonNaN.c -> .os [ SHCC] RISCV/ext/softfloat/s_f32UIToCommonNaN.c -> .os [ SHCC] RISCV/ext/softfloat/s_f64UIToCommonNaN.c -> .os [ SHCC] RISCV/ext/softfloat/s_le128.c -> .os [ SHCC] RISCV/ext/softfloat/s_lt128.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul128By32.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul128MTo256M.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul128To256M.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul64ByShifted32To128.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul64To128.c -> .os [ SHCC] RISCV/ext/softfloat/s_mul64To128M.c -> .os [ SHCC] RISCV/ext/softfloat/s_mulAddF128.c -> .os [ SHCC] RISCV/ext/softfloat/s_mulAddF16.c -> .os [ SHCC] RISCV/ext/softfloat/s_mulAddF32.c -> .os [ SHCC] RISCV/ext/softfloat/s_mulAddF64.c -> .os [ SHCC] RISCV/ext/softfloat/s_negXM.c -> .os [ SHCC] RISCV/ext/softfloat/s_normRoundPackToF128.c -> .os [ SHCC] RISCV/ext/softfloat/s_normRoundPackToF16.c -> .os [ SHCC] RISCV/ext/softfloat/s_normRoundPackToF32.c -> .os [ SHCC] RISCV/ext/softfloat/s_normRoundPackToF64.c -> .os [ SHCC] RISCV/ext/softfloat/s_normSubnormalF128Sig.c -> .os [ SHCC] RISCV/ext/softfloat/s_normSubnormalF16Sig.c -> .os [ SHCC] RISCV/ext/softfloat/s_normSubnormalF32Sig.c -> .os [ SHCC] RISCV/ext/softfloat/s_normSubnormalF64Sig.c -> .os [ SHCC] RISCV/ext/softfloat/softfloat_raiseFlags.c -> .os [ SHCC] RISCV/ext/softfloat/softfloat_state.c -> .os [ SHCC] RISCV/ext/softfloat/s_propagateNaNF128UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_propagateNaNF16UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_propagateNaNF32UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_propagateNaNF64UI.c -> .os [ SHCC] RISCV/ext/softfloat/s_remStepMBy32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundMToI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundMToUI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackMToI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackMToUI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToF128.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToF16.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToF32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToF64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToI32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToUI32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundPackToUI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundToI32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundToI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundToUI32.c -> .os [ SHCC] RISCV/ext/softfloat/s_roundToUI64.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam128.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam128Extra.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam256M.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam32.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam64.c -> .os [ SHCC] RISCV/ext/softfloat/s_shiftRightJam64Extra.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftLeft128.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftLeft64To96M.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRight128.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightExtendM.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam128.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam128Extra.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam64.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightJam64Extra.c -> .os [ SHCC] RISCV/ext/softfloat/s_shortShiftRightM.c -> .os [ SHCC] RISCV/ext/softfloat/s_sub128.c -> .os [ SHCC] RISCV/ext/softfloat/s_sub1XM.c -> .os [ SHCC] RISCV/ext/softfloat/s_sub256M.c -> .os [ SHCC] RISCV/ext/softfloat/s_subMagsF128.c -> .os [ SHCC] RISCV/ext/softfloat/s_subMagsF16.c -> .os [ SHCC] RISCV/ext/softfloat/s_subMagsF32.c -> .os [ SHCC] RISCV/ext/softfloat/s_subMagsF64.c -> .os [ SHCC] RISCV/ext/softfloat/s_subM.c -> .os [ SHCC] RISCV/ext/softfloat/ui32_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/ui32_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/ui32_to_f32.c -> .os [ SHCC] RISCV/ext/softfloat/ui32_to_f64.c -> .os [ SHCC] RISCV/ext/softfloat/ui64_to_f128.c -> .os [ SHCC] RISCV/ext/softfloat/ui64_to_f16.c -> .os [ SHCC] RISCV/ext/softfloat/ui64_to_f32.c -> .os [ SHCC] RISCV/ext/softfloat/ui64_to_f64.c -> .os build/RISCV/ext/libelf/native-elf-format > build/RISCV/ext/libelf/native-elf-format.h [ M4] RISCV/ext/libelf/elf_types.m4, libelf_convert.m4 -> libelf_convert.c [ SHCC] RISCV/ext/libelf/gelf_symshndx.c -> .os [ SHCC] RISCV/ext/libelf/elf_rawfile.c -> .os [ SHCC] RISCV/ext/libelf/libelf_extended.c -> .os [ SHCC] RISCV/ext/libelf/elf_rand.c -> .os [ SHCC] RISCV/ext/libelf/libelf_convert.c -> .os [ SHCC] RISCV/ext/libelf/elf_getarhdr.c -> .os [ SHCC] RISCV/ext/libelf/libelf_align.c -> .os [ SHCC] RISCV/ext/libelf/gelf_fsize.c -> .os [ SHCC] RISCV/ext/libelf/libelf_phdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_getident.c -> .os [ SHCC] RISCV/ext/libelf/elf_strptr.c -> .os [ SHCC] RISCV/ext/libelf/elf.c -> .os [ SHCC] RISCV/ext/libelf/libelf_ar_util.c -> .os [ SHCC] RISCV/ext/libelf/gelf_phdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_errmsg.c -> .os [ SHCC] RISCV/ext/libelf/elf_memory.c -> .os [ SHCC] RISCV/ext/libelf/gelf_syminfo.c -> .os [ SHCC] RISCV/ext/libelf/gelf_cap.c -> .os [ SHCC] RISCV/ext/libelf/libelf_ehdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_flag.c -> .os [ SHCC] RISCV/ext/libelf/elf_phnum.c -> .os [ SHCC] RISCV/ext/libelf/libelf.c -> .os [ SHCC] RISCV/ext/libelf/gelf_ehdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_shnum.c -> .os [ SHCC] RISCV/ext/libelf/libelf_open.c -> .os [ SHCC] RISCV/ext/libelf/elf_getbase.c -> .os [ SHCC] RISCV/ext/libelf/elf_shstrndx.c -> .os [ SHCC] RISCV/ext/libelf/libelf_ar.c -> .os [ SHCC] RISCV/ext/libelf/gelf_move.c -> .os [ SHCC] RISCV/ext/libelf/elf_end.c -> .os [ SHCC] RISCV/ext/libelf/libelf_xlate.c -> .os [ SHCC] RISCV/ext/libelf/elf_kind.c -> .os [ SHCC] RISCV/ext/libelf/gelf_sym.c -> .os [ SHCC] RISCV/ext/libelf/gelf_checksum.c -> .os [ SHCC] RISCV/ext/libelf/elf_version.c -> .os [ SHCC] RISCV/ext/libelf/elf_cntl.c -> .os [ SHCC] RISCV/ext/libelf/libelf_data.c -> .os [ SHCC] RISCV/ext/libelf/gelf_rela.c -> .os [ SHCC] RISCV/ext/libelf/elf_fill.c -> .os [ SHCC] RISCV/ext/libelf/elf_open.c -> .os [ SHCC] RISCV/ext/libelf/gelf_xlate.c -> .os [ SHCC] RISCV/ext/libelf/gelf_dyn.c -> .os [ SHCC] RISCV/ext/libelf/elf_scn.c -> .os [ SHCC] RISCV/ext/libelf/libelf_memory.c -> .os [ SHCC] RISCV/ext/libelf/elf_getarsym.c -> .os [ SHCC] RISCV/ext/libelf/libelf_allocate.c -> .os [ SHCC] RISCV/ext/libelf/gelf_getclass.c -> .os [ SHCC] RISCV/ext/libelf/elf_data.c -> .os [ SHCC] RISCV/ext/libelf/libelf_shdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_hash.c -> .os [ SHCC] RISCV/ext/libelf/gelf_shdr.c -> .os [ SHCC] RISCV/ext/libelf/elf_update.c -> .os [ SHCC] RISCV/ext/libelf/elf_begin.c -> .os [ SHCC] RISCV/ext/libelf/libelf_checksum.c -> .os [ SHCC] RISCV/ext/libelf/gelf_rel.c -> .os [ SHCC] RISCV/ext/libelf/elf_errno.c -> .os [ SHCC] RISCV/ext/libelf/elf_next.c -> .os [ AR] -> RISCV/ext/softfloat/libsoftfloat.a [ M4] RISCV/ext/libelf/elf_types.m4, libelf_fsize.m4 -> libelf_fsize.c [ M4] RISCV/ext/libelf/elf_types.m4, libelf_msize.m4 -> libelf_msize.c [ SHCC] RISCV/ext/libelf/libelf_fsize.c -> .os [ SHCC] RISCV/ext/libelf/libelf_msize.c -> .os [ AR] -> RISCV/ext/libelf/libelf.a [ RANLIB] -> RISCV/ext/softfloat/libsoftfloat.a [ RANLIB] -> RISCV/ext/libelf/libelf.a [ LINK] -> RISCV/gem5.opt scons: done building targets. Logging call to command: /nobackup/jenkins/workspace/weekly/build/ALL/gem5.opt -d /tmp/gem5out5w84u6rf -re --silent-redirect /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py --cpu atomic --num-cpus 1 --mem-system classic --dram-class DualChannelDDR4_2400 --boot-type systemd --resource-directory /nobackup/jenkins/workspace/weekly/tests/gem5/resources Logging call to command: /nobackup/jenkins/workspace/weekly/build/RISCV/gem5.opt -d /tmp/gem5outcjzzw9k5 -re --silent-redirect /nobackup/jenkins/workspace/weekly/configs/example/gem5_library/riscvmatched-fs.py Logging call to command: /nobackup/jenkins/workspace/weekly/build/ALL/gem5.opt -d /tmp/gem5outu7x7huo4 -re --silent-redirect /nobackup/jenkins/workspace/weekly/tests/gem5/configs/download_check.py --download-directory /nobackup/jenkins/workspace/weekly/tests/gem5/resources/resource-downloading-test Logging call to command: /nobackup/jenkins/workspace/weekly/build/ALL/gem5.opt -d /tmp/gem5outoufrp9wv -re --silent-redirect /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py --cpu atomic --num-cpus 2 --mem-system classic --dram-class DualChannelDDR4_2400 --boot-type systemd --resource-directory /nobackup/jenkins/workspace/weekly/tests/gem5/resources Logging call to command: /nobackup/jenkins/workspace/weekly/build/ALL/gem5.opt -d /tmp/gem5outrysmrn45 -re --silent-redirect /nobackup/jenkins/workspace/weekly/tests/gem5/configs/x86_boot_exit_run.py --cpu timing --num-cpus 1 --mem-system classic --dram-class DualChannelDDR4_2400 --boot-type systemd --resource-directory /nobackup/jenkins/workspace/weekly/tests/gem5/resources Starting Test Suite: atomic-cpu_1-cores_classic_DualChannelDDR4_2400_systemd_x86-boot-test-ALL-x86_64-opt Starting Test Case: atomic-cpu_1-cores_classic_DualChannelDDR4_2400_systemd_x86-boot-test-ALL-x86_64-opt Starting Test Suite: test-gem5-library-example-riscvmatched-fs-RISCV-x86_64-opt Starting Test Case: test-gem5-library-example-riscvmatched-fs-RISCV-x86_64-opt Starting Test Suite: test-resource-downloading-ALL-x86_64-opt Starting Test Case: test-resource-downloading-ALL-x86_64-opt Starting Test Suite: atomic-cpu_2-cores_classic_DualChannelDDR4_2400_systemd_x86-boot-test-ALL-x86_64-opt Starting Test Case: atomic-cpu_2-cores_classic_DualChannelDDR4_2400_systemd_x86-boot-test-ALL-x86_64-opt Build step 'Execute shell' marked build as failure Archiving artifacts _______________________________________________ gem5-dev mailing list -- [email protected] To unsubscribe send an email to [email protected]
