Giacomo Travaglini has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65174?usp=email )
Change subject: arch-arm: Setup ISA::gicv3CpuInterface on demand only
......................................................................
arch-arm: Setup ISA::gicv3CpuInterface on demand only
This is aligning with what we are already doing with the CoreTimers:
rather than setting up the interface at ISA::startup, we set it
up on the first time the GIC cpu interface is actually required
by the ISA
Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
1 file changed, 26 insertions(+), 11 deletions(-)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..50c88ac 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -523,16 +523,6 @@
return;
selfDebug->init(tc);
-
- Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
- if (!gicv3)
- return;
-
- if (!gicv3CpuInterface)
- gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
- gicv3CpuInterface->setISA(this);
- gicv3CpuInterface->setThreadContext(tc);
}
void
@@ -2008,7 +1998,17 @@
BaseISADevice &
ISA::getGICv3CPUInterface()
{
- panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
+ if (gicv3CpuInterface)
+ return *gicv3CpuInterface.get();
+
+ assert(system);
+ Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
+ assert(gicv3);
+
+ gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
+ gicv3CpuInterface->setISA(this);
+ gicv3CpuInterface->setThreadContext(tc);
+
return *gicv3CpuInterface.get();
}
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Iec29b2098ea29ca2886a69c5db8a2bc8d2f6f71e
Gerrit-Change-Number: 65174
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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