[gem5-dev] [S] Change in gem5/gem5[develop]: dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

[Giacomo Travaglini (Gerrit) via gem5-dev]

Giacomo Travaglini has uploaded this change for review. (  
https://gem5-review.googlesource.com/c/public/gem5/+/65291?usp=email )

Change subject: dev-arm: Setup TC/ISA at construction time of  
Gicv3CPUInterface
......................................................................

dev-arm: Setup TC/ISA at construction time of Gicv3CPUInterface

We should initialize them as soon as possible to make sure
any Gicv3CPUInterface method uses a valid reference

Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
---
M src/arch/arm/isa.cc
M src/dev/arm/gic_v3.cc
M src/dev/arm/gic_v3_cpu_interface.cc
M src/dev/arm/gic_v3_cpu_interface.hh
4 files changed, 23 insertions(+), 19 deletions(-)



diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index a30fd94..3aabb56 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -530,9 +530,6 @@

     if (!gicv3CpuInterface)
         gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
-
-    gicv3CpuInterface->setISA(this);
-    gicv3CpuInterface->setThreadContext(tc);
 }

 void
diff --git a/src/dev/arm/gic_v3.cc b/src/dev/arm/gic_v3.cc
index dde3818..e14d1f2 100644
--- a/src/dev/arm/gic_v3.cc
+++ b/src/dev/arm/gic_v3.cc
@@ -147,7 +147,7 @@

     for (int i = 0; i < threads; i++) {
         redistributors[i] = new Gicv3Redistributor(this, i);
-        cpuInterfaces[i] = new Gicv3CPUInterface(this, i);
+        cpuInterfaces[i] = new Gicv3CPUInterface(this, sys->threads[i]);
     }

     distRange = RangeSize(params().dist_addr,
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc  
b/src/dev/arm/gic_v3_cpu_interface.cc
index 0e1dbaa..a11dd9b 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -55,15 +55,19 @@
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR;
 const uint8_t Gicv3CPUInterface::GIC_MIN_BPR_NS;

-Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id)
+Gicv3CPUInterface::Gicv3CPUInterface(Gicv3 * gic, ThreadContext *_tc)
     : BaseISADevice(),
       gic(gic),
       redistributor(nullptr),
       distributor(nullptr),
-      cpuId(cpu_id)
+      tc(_tc),
+      maintenanceInterrupt(gic->params().maint_int->get(tc)),
+      cpuId(tc->contextId())
 {
     hppi.prio = 0xff;
     hppi.intid = Gicv3::INTID_SPURIOUS;
+
+    setISA(static_cast<ISA*>(tc->getIsaPtr()));
 }

 void
@@ -80,15 +84,6 @@
         hppi.prio = 0xff;
 }

-void
-Gicv3CPUInterface::setThreadContext(ThreadContext *_tc)
-{
-    tc = _tc;
-    maintenanceInterrupt = gic->params().maint_int->get(tc);
-    fatal_if(maintenanceInterrupt->num() >=  
redistributor->irqPending.size(),
-        "Invalid maintenance interrupt number\n");
-}
-
 bool
 Gicv3CPUInterface::getHCREL2FMO() const
 {
diff --git a/src/dev/arm/gic_v3_cpu_interface.hh  
b/src/dev/arm/gic_v3_cpu_interface.hh
index e860373..c39fab7 100644
--- a/src/dev/arm/gic_v3_cpu_interface.hh
+++ b/src/dev/arm/gic_v3_cpu_interface.hh
@@ -68,10 +68,10 @@
     Gicv3 * gic;
     Gicv3Redistributor * redistributor;
     Gicv3Distributor * distributor;
-    uint32_t cpuId;

-    ArmInterruptPin *maintenanceInterrupt;
     ThreadContext *tc;
+    ArmInterruptPin *maintenanceInterrupt;
+    uint32_t cpuId;

     BitUnion64(ICC_CTLR_EL1)
         Bitfield<63, 20> res0_3;
@@ -359,7 +359,7 @@
     void setBankedMiscReg(ArmISA::MiscRegIndex misc_reg, RegVal val) const;
   public:

-    Gicv3CPUInterface(Gicv3 * gic, uint32_t cpu_id);
+    Gicv3CPUInterface(Gicv3 * gic, ThreadContext *tc);

     void init();

@@ -369,7 +369,6 @@
   public: // BaseISADevice
     RegVal readMiscReg(int misc_reg) override;
     void setMiscReg(int misc_reg, RegVal val) override;
-    void setThreadContext(ThreadContext *tc) override;
 };

 } // namespace gem5

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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I8fffebdab9136a9027c4f61bb9413e97031e1969
Gerrit-Change-Number: 65291
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-MessageType: newchange
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