Roger Chang has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/65533?usp=email )
Change subject: RV32 tests
......................................................................
RV32 tests
Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
---
M tests/gem5/asmtest/tests.py
A tests/gem5/configs/riscv_binary_run.py
2 files changed, 232 insertions(+), 143 deletions(-)
diff --git a/tests/gem5/asmtest/tests.py b/tests/gem5/asmtest/tests.py
index b2a5992..9f3e065 100644
--- a/tests/gem5/asmtest/tests.py
+++ b/tests/gem5/asmtest/tests.py
@@ -26,153 +26,31 @@
from testlib import *
-if config.bin_path:
- resource_path = config.bin_path
-else:
- resource_path = joinpath(absdirpath(__file__), "..", "resources")
+import glob
+import os
# The following lists the RISCV binaries. Those commented out presently
result
# in a test failure. This is outlined in the following Jira issue:
# https://gem5.atlassian.net/browse/GEM5-496
-binaries = (
- "rv64samt-ps-sysclone_d",
- "rv64samt-ps-sysfutex1_d",
- # 'rv64samt-ps-sysfutex2_d',
- "rv64samt-ps-sysfutex3_d",
- # 'rv64samt-ps-sysfutex_d',
- "rv64ua-ps-amoadd_d",
- "rv64ua-ps-amoadd_w",
- "rv64ua-ps-amoand_d",
- "rv64ua-ps-amoand_w",
- "rv64ua-ps-amomax_d",
- "rv64ua-ps-amomax_w",
- "rv64ua-ps-amomaxu_d",
- "rv64ua-ps-amomaxu_w",
- "rv64ua-ps-amomin_d",
- "rv64ua-ps-amomin_w",
- "rv64ua-ps-amominu_d",
- "rv64ua-ps-amominu_w",
- "rv64ua-ps-amoor_d",
- "rv64ua-ps-amoor_w",
- "rv64ua-ps-amoswap_d",
- "rv64ua-ps-amoswap_w",
- "rv64ua-ps-amoxor_d",
- "rv64ua-ps-amoxor_w",
- "rv64ua-ps-lrsc",
- "rv64uamt-ps-amoadd_d",
- "rv64uamt-ps-amoand_d",
- "rv64uamt-ps-amomax_d",
- "rv64uamt-ps-amomaxu_d",
- "rv64uamt-ps-amomin_d",
- "rv64uamt-ps-amominu_d",
- "rv64uamt-ps-amoor_d",
- "rv64uamt-ps-amoswap_d",
- "rv64uamt-ps-amoxor_d",
- "rv64uamt-ps-lrsc_d",
- "rv64ud-ps-fadd",
- "rv64ud-ps-fclass",
- "rv64ud-ps-fcmp",
- "rv64ud-ps-fcvt",
- "rv64ud-ps-fcvt_w",
- "rv64ud-ps-fdiv",
- "rv64ud-ps-fmadd",
- "rv64ud-ps-fmin",
- "rv64ud-ps-ldst",
- "rv64ud-ps-move",
- "rv64ud-ps-recoding",
- "rv64ud-ps-structural",
- "rv64uf-ps-fadd",
- "rv64uf-ps-fclass",
- "rv64uf-ps-fcmp",
- "rv64uf-ps-fcvt",
- "rv64uf-ps-fcvt_w",
- "rv64uf-ps-fdiv",
- "rv64uf-ps-fmadd",
- "rv64uf-ps-fmin",
- "rv64uf-ps-ldst",
- "rv64uf-ps-move",
- "rv64uf-ps-recoding",
- "rv64ui-ps-add",
- "rv64ui-ps-addi",
- "rv64ui-ps-addiw",
- "rv64ui-ps-addw",
- "rv64ui-ps-and",
- "rv64ui-ps-andi",
- "rv64ui-ps-auipc",
- "rv64ui-ps-beq",
- "rv64ui-ps-bge",
- "rv64ui-ps-bgeu",
- "rv64ui-ps-blt",
- "rv64ui-ps-bltu",
- "rv64ui-ps-bne",
- "rv64ui-ps-fence_i",
- "rv64ui-ps-jal",
- "rv64ui-ps-jalr",
- "rv64ui-ps-lb",
- "rv64ui-ps-lbu",
- "rv64ui-ps-ld",
- "rv64ui-ps-lh",
- "rv64ui-ps-lhu",
- "rv64ui-ps-lui",
- "rv64ui-ps-lw",
- "rv64ui-ps-lwu",
- "rv64ui-ps-or",
- "rv64ui-ps-ori",
- "rv64ui-ps-sb",
- "rv64ui-ps-sd",
- "rv64ui-ps-sh",
- "rv64ui-ps-simple",
- "rv64ui-ps-sll",
- "rv64ui-ps-slli",
- "rv64ui-ps-slliw",
- "rv64ui-ps-sllw",
- "rv64ui-ps-slt",
- "rv64ui-ps-slti",
- "rv64ui-ps-sltiu",
- "rv64ui-ps-sltu",
- "rv64ui-ps-sra",
- "rv64ui-ps-srai",
- "rv64ui-ps-sraiw",
- "rv64ui-ps-sraw",
- "rv64ui-ps-srl",
- "rv64ui-ps-srli",
- "rv64ui-ps-srliw",
- "rv64ui-ps-srlw",
- "rv64ui-ps-sub",
- "rv64ui-ps-subw",
- "rv64ui-ps-sw",
- "rv64ui-ps-xor",
- "rv64ui-ps-xori",
- "rv64um-ps-div",
- "rv64um-ps-divu",
- "rv64um-ps-divuw",
- "rv64um-ps-divw",
- "rv64um-ps-mul",
- "rv64um-ps-mulh",
- "rv64um-ps-mulhsu",
- "rv64um-ps-mulhu",
- "rv64um-ps-mulw",
- "rv64um-ps-rem",
- "rv64um-ps-remu",
- "rv64um-ps-remuw",
- "rv64um-ps-remw",
- "rv64uzfh-ps-fadd",
- "rv64uzfh-ps-fclass",
- "rv64uzfh-ps-fcmp",
- "rv64uzfh-ps-fcvt",
- "rv64uzfh-ps-fcvt_w",
- "rv64uzfh-ps-fdiv",
- "rv64uzfh-ps-fmadd",
- "rv64uzfh-ps-fmin",
- "rv64uzfh-ps-ldst",
- "rv64uzfh-ps-move",
- "rv64uzfh-ps-recoding",
-)
+riscv_tests = '/opt/riscv/target/share/riscv-tests'
+binaries64_path = glob.glob(os.path.join(riscv_tests, 'isa/rv64*-ps*'))
+binaries64_path = sorted(list(filter(
+ lambda path: not path.endswith('.dump'),
+ binaries64_path,
+)))
+
+binaries32_path = glob.glob(os.path.join(riscv_tests, 'isa/rv32*-ps*'))
+binaries32_path = sorted(list(filter(
+ lambda path: not path.endswith('.dump'),
+ binaries32_path,
+)))
cpu_types = ("atomic", "timing", "minor", "o3")
for cpu_type in cpu_types:
- for binary in binaries:
+ for path in binaries64_path:
+ binary = os.path.basename(path)
+ bindir = os.path.dirname(path)
gem5_verify_config(
name=f"asm-riscv-{binary}-{cpu_type}",
verifiers=(),
@@ -181,17 +59,46 @@
"tests",
"gem5",
"configs",
- "simple_binary_run.py",
+ "riscv_binary_run.py",
),
config_args=[
binary,
cpu_type,
- "riscv",
+ "64",
"--num-cores",
"4",
"--resource-directory",
- resource_path,
+ bindir,
+ "--no-download",
],
- valid_isas=(constants.all_compiled_tag,),
+ valid_isas=(constants.all_compiled_tag, constants.riscv_tag),
+ valid_hosts=constants.supported_hosts,
+ )
+
+for cpu_type in cpu_types:
+ for path in binaries32_path:
+ binary = os.path.basename(path)
+ bindir = os.path.dirname(path)
+ gem5_verify_config(
+ name=f"asm-riscv-{binary}-{cpu_type}",
+ verifiers=(),
+ config=joinpath(
+ config.base_dir,
+ "tests",
+ "gem5",
+ "configs",
+ "riscv_binary_run.py",
+ ),
+ config_args=[
+ binary,
+ cpu_type,
+ "32",
+ "--num-cores",
+ "4",
+ "--resource-directory",
+ bindir,
+ "--no-download",
+ ],
+ valid_isas=(constants.all_compiled_tag, constants.riscv_tag),
valid_hosts=constants.supported_hosts,
)
diff --git a/tests/gem5/configs/riscv_binary_run.py
b/tests/gem5/configs/riscv_binary_run.py
new file mode 100644
index 0000000..810b793
--- /dev/null
+++ b/tests/gem5/configs/riscv_binary_run.py
@@ -0,0 +1,173 @@
+# Copyright (c) 2021 The Regents of the University of California
+# Copyright (c) 2022 Google Inc
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+"""
+A run script for a very simple Syscall-Execution running simple binaries.
+The system has no cache heirarchy and is as "bare-bones" as you can get in
+gem5 while still being functinal.
+"""
+
+from gem5.resources.resource import CustomResource, Resource
+from gem5.components.processors.cpu_types import (
+ get_cpu_types_str_set,
+ get_cpu_type_from_str,
+ CPUTypes,
+)
+from gem5.components.memory import SingleChannelDDR3_1600
+from gem5.components.boards.simple_board import SimpleBoard
+from gem5.components.cachehierarchies.classic.no_cache import NoCache
+from gem5.components.processors.base_cpu_processor import BaseCPUProcessor
+from gem5.components.boards.mem_mode import MemMode
+from gem5.components.processors.cpu_types import CPUTypes
+from gem5.simulate.simulator import Simulator
+from gem5.isas import ISA
+
+import m5
+
+import argparse
+import importlib
+import os
+import sys
+
+from python.gem5.components.processors.base_cpu_core import BaseCPUCore
+
+cpu_types_string_map = {
+ CPUTypes.ATOMIC: "AtomicSimpleCPU",
+ CPUTypes.O3: "O3CPU",
+ CPUTypes.TIMING: "TimingSimpleCPU",
+ CPUTypes.KVM: "KvmCPU",
+ CPUTypes.MINOR: "MinorCPU",
+}
+
+parser = argparse.ArgumentParser(
+ description="A gem5 script for running simple binaries in SE mode."
+)
+
+parser.add_argument(
+ "resource", type=str, help="The gem5 resource binary to run."
+)
+
+parser.add_argument(
+ "cpu", type=str, choices=get_cpu_types_str_set(), help="The CPU type
used."
+)
+
+parser.add_argument(
+ "bits", type=int, choices=[32, 64], help="binary bits"
+)
+
+parser.add_argument(
+ "-b",
+ "--base-cpu-processor",
+ action="store_true",
+ help="Use the BaseCPUProcessor instead of the SimpleProcessor.",
+)
+
+parser.add_argument(
+ "-r",
+ "--resource-directory",
+ type=str,
+ required=False,
+ help="The directory in which resources will be downloaded or exist.",
+)
+
+parser.add_argument(
+ "--arguments",
+ type=str,
+ action="append",
+ default=[],
+ required=False,
+ help="The input arguments for the binary.",
+)
+
+parser.add_argument(
+ "-n",
+ "--num-cores",
+ type=int,
+ default=1,
+ required=False,
+ help="The number of CPU cores to run.",
+)
+
+parser.add_argument(
+ "--no-download",
+ dest="download",
+ action="store_false",
+ default=True,
+ help="download from dist"
+)
+
+args = parser.parse_args()
+
+if args.download:
+ binary = Resource(args.resource,
resource_directory=args.resource_directory)
+else:
+ binary = CustomResource(os.path.join(args.resource_directory,
args.resource))
+
+# Setup the system.
+cache_hierarchy = NoCache()
+memory = SingleChannelDDR3_1600()
+
+if args.bits == 32:
+ class_str =
f"Riscv32{cpu_types_string_map[get_cpu_type_from_str(args.cpu)]}"
+else:
+ class_str =
f"Riscv{cpu_types_string_map[get_cpu_type_from_str(args.cpu)]}"
+
+m5_objects = importlib.import_module('m5.objects')
+cpu_class = getattr(m5_objects, class_str)
+cores = [
+ BaseCPUCore(
+ core=cpu_class(cpu_id=i),
+ isa=ISA.RISCV,
+ )
+ for i in range(args.num_cores)
+]
+
+processor = BaseCPUProcessor(
+ cores=cores,
+)
+
+motherboard = SimpleBoard(
+ clk_freq="3GHz",
+ processor=processor,
+ memory=memory,
+ cache_hierarchy=cache_hierarchy,
+)
+
+# Set the workload
+motherboard.set_se_binary_workload(binary, arguments=args.arguments)
+
+# Run the simulation
+simulator = Simulator(board=motherboard)
+simulator.run()
+
+print(
+ "Exiting @ tick {} because {}.".format(
+ simulator.get_current_tick(), simulator.get_last_exit_event_cause()
+ )
+)
+
+sys.exit(simulator._last_exit_event.getCode())
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I5cc4c2eeb7654a4acc2d167eb76d8b6522e65dd9
Gerrit-Change-Number: 65533
Gerrit-PatchSet: 1
Gerrit-Owner: Roger Chang <[email protected]>
Gerrit-MessageType: newchange
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