Yu-hsin Wang has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email )
Change subject: fastmodel: CortexR52 export standbywfi signal
......................................................................
fastmodel: CortexR52 export standbywfi signal
Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65534
Reviewed-by: Gabe Black <[email protected]>
Tested-by: kokoro <[email protected]>
Maintainer: Gabe Black <[email protected]>
---
M src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
M src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
M src/arch/arm/fastmodel/CortexR52/evs.cc
M src/arch/arm/fastmodel/CortexR52/evs.hh
M src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
M src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
M src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
M src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
M src/arch/arm/fastmodel/common/signal_receiver.hh
9 files changed, 85 insertions(+), 1 deletion(-)
Approvals:
Gabe Black: Looks good to me, approved; Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
index 4970ae2..1e267f0 100644
--- a/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
+++ b/src/arch/arm/fastmodel/CortexR52/FastModelCortexR52.py
@@ -31,7 +31,7 @@
from m5.objects.ArmISA import ArmISA
from m5.objects.FastModel import AmbaInitiatorSocket, AmbaTargetSocket
from m5.objects.ResetPort import ResetResponsePort
-from m5.objects.IntPin import IntSinkPin, VectorIntSinkPin
+from m5.objects.IntPin import IntSourcePin, IntSinkPin, VectorIntSinkPin
from m5.objects.Iris import IrisBaseCPU
from m5.objects.SystemC import SystemC_ScModule
@@ -56,6 +56,9 @@
"processor logic, including debug logic."
)
halt = IntSinkPin("Raising this signal will put the core into halt
mode.")
+ standbywfi = IntSourcePin(
+ "This signal indicates if a core is in WFI state."
+ )
CFGEND = Param.Bool(
False,
diff --git a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
index be83082..9dfe7a5 100644
--- a/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
+++ b/src/arch/arm/fastmodel/CortexR52/cortex_r52.cc
@@ -92,6 +92,10 @@
// Since PPIs are indexed both by core and by number, modify the
name
// to hold the core number.
return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
+ } else if (if_name == "standbywfi") {
+ // Since standbywfi is indexed by fanout, modify the name to hold
the
+ // core number.
+ return evs->gem5_getPort(csprintf("%s_%d", if_name, num), idx);
} else if (if_name == "amba" || if_name == "llpp" || if_name
== "flash" ||
if_name == "core_reset" || if_name == "poweron_reset" ||
if_name == "halt") {
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.cc
b/src/arch/arm/fastmodel/CortexR52/evs.cc
index 6887c6c..734323e 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.cc
+++ b/src/arch/arm/fastmodel/CortexR52/evs.cc
@@ -79,6 +79,7 @@
core_reset(name + ".core_reset", 0),
poweron_reset(name + ".poweron_reset", 0),
halt(name + ".halt", 0),
+ standbywfi(name + ".standbywfi"),
cfgvectable((name + "cfgvectable").c_str())
{
for (int i = 0; i < Evs::PpiCount; i++) {
@@ -88,6 +89,7 @@
core_reset.signal_out.bind(evs->core_reset[cpu]);
poweron_reset.signal_out.bind(evs->poweron_reset[cpu]);
halt.signal_out.bind(evs->halt[cpu]);
+ evs->standbywfi[cpu].bind(standbywfi.signal_in);
cfgvectable.bind(evs->cfgvectable[cpu]);
}
@@ -161,6 +163,14 @@
panic("Couldn't find CPU number in %s.", if_name);
}
return *this->corePins.at(cpu)->ppis.at(idx);
+ } else if (if_name.substr(0, 10) == "standbywfi") {
+ int cpu;
+ try {
+ cpu = std::stoi(if_name.substr(11));
+ } catch (const std::invalid_argument &a) {
+ panic("Couldn't find CPU number in %s.", if_name);
+ }
+ return this->corePins.at(cpu)->standbywfi.getSignalOut(idx);
} else {
return Base::gem5_getPort(if_name, idx);
}
diff --git a/src/arch/arm/fastmodel/CortexR52/evs.hh
b/src/arch/arm/fastmodel/CortexR52/evs.hh
index 535d678..02ef1ae 100644
--- a/src/arch/arm/fastmodel/CortexR52/evs.hh
+++ b/src/arch/arm/fastmodel/CortexR52/evs.hh
@@ -110,6 +110,7 @@
SignalSender core_reset;
SignalSender poweron_reset;
SignalSender halt;
+ SignalReceiverInt standbywfi;
SignalInitiator<uint64_t> cfgvectable;
};
diff --git a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
index 2a7299d..2738ba2 100644
--- a/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x1/x1.lisa
@@ -53,6 +53,9 @@
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
+ // Status signals.
+ core.standbywfi => self.standbywfi;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -79,6 +82,7 @@
slave port<Signal> core_reset[1];
slave port<Signal> poweron_reset[1];
slave port<Signal> halt[1];
+ master port<Signal> standbywfi[1];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[1];
diff --git a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
index 9100a5b..485ffee 100644
--- a/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x2/x2.lisa
@@ -53,6 +53,9 @@
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
+ // Status signals.
+ core.standbywfi => self.standbywfi;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -80,6 +83,7 @@
slave port<Signal> core_reset[2];
slave port<Signal> poweron_reset[2];
slave port<Signal> halt[2];
+ master port<Signal> standbywfi[2];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[2];
diff --git a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
index bb8d153..1e526d9 100644
--- a/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x3/x3.lisa
@@ -53,6 +53,9 @@
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
+ // Status signals.
+ core.standbywfi => self.standbywfi;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -81,6 +84,7 @@
slave port<Signal> core_reset[3];
slave port<Signal> poweron_reset[3];
slave port<Signal> halt[3];
+ master port<Signal> standbywfi[3];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[3];
diff --git a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
index 5b278dd..df23bf1 100644
--- a/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexR52/x4/x4.lisa
@@ -53,6 +53,9 @@
self.dbg_reset => core.presetdbg;
self.halt => core.cpuhalt;
+ // Status signals.
+ core.standbywfi => self.standbywfi;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -82,6 +85,7 @@
slave port<Signal> core_reset[4];
slave port<Signal> poweron_reset[4];
slave port<Signal> halt[4];
+ master port<Signal> standbywfi[4];
slave port<Signal> top_reset;
slave port<Signal> dbg_reset;
slave port<Value_64> cfgvectable[4];
diff --git a/src/arch/arm/fastmodel/common/signal_receiver.hh
b/src/arch/arm/fastmodel/common/signal_receiver.hh
index 0025e39..9907877 100644
--- a/src/arch/arm/fastmodel/common/signal_receiver.hh
+++ b/src/arch/arm/fastmodel/common/signal_receiver.hh
@@ -34,8 +34,12 @@
#pragma GCC diagnostic pop
#include <functional>
+#include <vector>
#include "base/compiler.hh"
+#include "base/cprintf.hh"
+#include "base/types.hh"
+#include "dev/intpin.hh"
namespace gem5
{
@@ -80,6 +84,39 @@
}
};
+class SignalReceiverInt : public SignalReceiver
+{
+ public:
+ using IntPin = IntSourcePin<SignalReceiverInt>;
+
+ explicit SignalReceiverInt(const std::string &name)
+ : SignalReceiver(name)
+ {
+ onChange([this](bool status) {
+ for (auto &signal : signalOut) {
+ if (signal && signal->isConnected())
+ status ? signal->raise() : signal->lower();
+ }
+ });
+ }
+
+ IntPin &
+ getSignalOut(int idx)
+ {
+ if (signalOut.size() <= idx) {
+ signalOut.resize(idx + 1);
+ }
+ if (!signalOut[idx]) {
+ signalOut[idx] = std::make_unique<IntPin>(
+ csprintf("%s.signalOut[%d]", get_name(), idx), idx, this);
+ }
+ return *signalOut[idx];
+ }
+
+ private:
+ std::vector<std::unique_ptr<IntPin>> signalOut;
+};
+
} // namespace fastmodel
} // namespace gem5
--
To view, visit
https://gem5-review.googlesource.com/c/public/gem5/+/65534?usp=email
To unsubscribe, or for help writing mail filters, visit
https://gem5-review.googlesource.com/settings
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ic9ed9a3e35f068e151725d36e7fff391013ff5d1
Gerrit-Change-Number: 65534
Gerrit-PatchSet: 7
Gerrit-Owner: Yu-hsin Wang <[email protected]>
Gerrit-Reviewer: Earl Ou <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Gabe Black <[email protected]>
Gerrit-Reviewer: Yu-hsin Wang <[email protected]>
Gerrit-Reviewer: kokoro <[email protected]>
Gerrit-CC: Han-sheng Liu <[email protected]>
Gerrit-MessageType: merged
_______________________________________________
gem5-dev mailing list -- [email protected]
To unsubscribe send an email to [email protected]
