Gabe Black has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/67571?usp=email )
Change subject: arch-riscv: Get rid of redundant reset fault invocation.
......................................................................
arch-riscv: Get rid of redundant reset fault invocation.
It was added in one change, another pending change which also added it
was rebased on top of it, and the redundant addition was left in when
the second change was submitted.
Change-Id: I3faf53bca983d8568af45ec7174c2a064eadc0a6
---
M src/arch/riscv/bare_metal/fs_workload.cc
1 file changed, 13 insertions(+), 5 deletions(-)
diff --git a/src/arch/riscv/bare_metal/fs_workload.cc
b/src/arch/riscv/bare_metal/fs_workload.cc
index 83f5411..4f7adb3 100644
--- a/src/arch/riscv/bare_metal/fs_workload.cc
+++ b/src/arch/riscv/bare_metal/fs_workload.cc
@@ -59,11 +59,6 @@
{
Workload::initState();
- for (auto *tc: system->threads) {
- RiscvISA::Reset().invoke(tc);
- tc->activate();
- }
-
warn_if(!bootloader->buildImage().write(system->physProxy),
"Could not load sections to memory.");
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I3faf53bca983d8568af45ec7174c2a064eadc0a6
Gerrit-Change-Number: 67571
Gerrit-PatchSet: 1
Gerrit-Owner: Gabe Black <gabe.bl...@gmail.com>
Gerrit-CC: Gabe Black <gabebl...@google.com>
Gerrit-MessageType: newchange
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