See <https://jenkins.gem5.org/job/weekly/110/display/redirect?page=changes>
Changes: [weihanchen] fastmodel: change the constructor of bridges [weihanchen] fastmodel: forward stream ID to gem5 [gabe.black] fastmodel: Export the reset signals of the GIC. [gabriel.busnot] dev-amdgpu: Patch forgotten port after mem port owner deprecation [shunhsingou] mem: use default backdoor behavior for thread_bridge [shunhsingou] sim: handle async events in main thread only [melissakjost] tests: Update testing documentation [gabe.black] dev: Add a definition for VectorResetResponsePort. [gabe.black] cpu: Add a generic model_reset port on the BaseCPU. [zhongcy93] arch-riscv: Fix the CSR instruction behavior. [matthew.poremba] arch-vega: Implement ds_write_b8_d16_hi [matthew.poremba] arch-vega: Make VGPR-offset for global SGPR-base signed [seanyukigeek] ext: Fix typo in DRAMSIM2 Sconscript [seanyukigeek] mem-dram: Make sure SHOW_SIM_OUTPUT is in global namespace. [matthew.poremba] dev-amdgpu: Fix address in POLL_REGMEM SDMA packet [matthew.poremba] arch-vega: Implementing global_atomic_or [matthew.poremba] arch-vega: Implementing global_atomic_smin [matthew.poremba] arch-vega: Implementing global_atomic_smax [matthew.poremba] dev-amdgpu: Update deprecated ports [hungweihsu] dev: add method to set initial register value out of constructor. [rogerycchang] arch-riscv: Fix the behavior of write to status CSR [rogerycchang] arch-riscv: Fix incorrect trap value of instruction fault [matthew.poremba] arch-vega: Update API for some flat atomics [yanlee] base: add extensible type [nikos.nikoleris] python: Ensure that m5.internal.params is available [yanlee] mem: add extension mechanism into Packet [yanlee] mem: add extension mechanism into Request [yanlee] base: extensible: add example codes of extension [turasov.ivan] arch-arm: Add missing <array> header in regs/misc.hh [Bobby R. Bruce] configs: Deprecate fs.py and se.py scripts [ztqiu] stdlib: Specialize the gem5-resources [ztqiu] stdlib: Add null/None versioning in resources.json [ztqiu] stdlib: Update resources to have downloads optional [ztqiu] stdlib: Implement Simpoint Resources [ztqiu] base,python: Added PcCountPair type and parameter [ztqiu] sim: Added PcCountTracker and PcCountTrackerManager [ztqiu] stdlib: Added stdlib LoopPoint classes [ztqiu] stdlib: Allow se_binary_workload to setup LoopPoints [ztqiu] stdlib: Added LoopPoint checkpoint specific generator [Bobby R. Bruce] stdlib: Change the default Looppoint JSON output to m5out [Bobby R. Bruce] stdlib: Update LoopPointRestore to take singular region_id [Bobby R. Bruce] stdlib: Add looppoint example scripts [Bobby R. Bruce] stdlib: Refactor Looppoint [Bobby R. Bruce] tests: Add pyunit tests for Looppoint [Bobby R. Bruce] tests: Incorporate Looppoint example scripts into TestLib [Bobby R. Bruce] stdlib: Add the LooppointCsvResource resource [Bobby R. Bruce] stdlib: Add LooppointJsonResource resource [Bobby R. Bruce] configs stdlib: Update checkpoint resource for riscv-hello [Bobby R. Bruce] configs,stdlib: Update simpoint-se-restore checkpoint [Bobby R. Bruce] stdlib: Fix checkpoint setting through set_workload func [Bobby R. Bruce] configs,stdlib: Add Workloads to Looppoint examples [rogerycchang] arch-riscv,dev: Fix behavior issues of PLIC [Jason Lowe-Power] cpu: Add fatal in BaseCPU for wrong workloads [Bobby R. Bruce] arch-x86,sim-se: Ignore the some mem syscalls [Bobby R. Bruce] stdlib: Add support for ELFies [Jason Lowe-Power] stdlib: Add progress bars for long functions [tom.rollet] cpu-o3: fix false positive in AddressSanitizer [rogerycchang] arch-riscv,dev: Add PLIC abstract class to support multiple PLIC [rogerycchang] arch-riscv,dev: Add HiFive Base Platform [gabe.black] mem: Add a parameter which will make a memory truly a ROM. [mkjost] cpu: Allow PcCountTracker to compile in NULL ISA [mkjost] base: Fix gcc-13 build error [handsomeliu] base: support calculating the intersection of two AddrRange [mkjost] arch-riscv: Revert CSR instruction fixes [Bobby R. Bruce] cpu: Move fetch stats from simple and minor to base [Bobby R. Bruce] cpu: Move execute stats from simple and minor to base [Bobby R. Bruce] cpu: Move commit stats from simple to base cpu [Bobby R. Bruce] cpu: Move numInsts, numOps, ipc, cpi to BaseCPU [Bobby R. Bruce] cpu-o3: Use base instructions committed counters in O3CPU [Bobby R. Bruce] cpu-o3: Move general fetch stats to BaseCPU::FetchCPUStats [Bobby R. Bruce] cpu-o3: Move O3 IEW stats to BaseCPU::ExecuteCPUStats [Bobby R. Bruce] cpu-kvm: Implement IPC and CPI base stats for KVM CPU [rogerycchang] arch-riscv: Support PMP lock feature [mattdsinclair] tests: cleanup m5out directly in weekly [alexrichardson] tests: Fix GCC -W(maybe-)uninitialized warnings [Bobby R. Bruce] cpu: Revert CPU stats changes [drinkcat] fastmodel: Check early for license server issue [kunpai] configs: Adds an example script for POWER Hello [alexrichardson] tests: Fix import path in simple_binary_run.py [alexrichardson] arch-riscv: Fix invalid std::map access [hoanguyen] stdlib: Fix bug in MESI_Three_Level_Cache initialization [hoanguyen] stdlib: use atomic_noncaching when using AtomicSimpleCPU with Ruby [gabriel.busnot] base: Create a gem5 type_traits.hh header [gabriel.busnot] sim: Define a new MemberEventWrapper event class [gabriel.busnot] sim: Switch from EventWrapper to MemberEventWrapper before deprec [gabriel.busnot] sim: Deprecate EventWrapper in favour of MemberEventWrapper [gabriel.busnot] sim: Use ref constructor of MemberEventWrapper everywhere [gabriel.busnot] sim: Deprecate pointer version of MemberEventWrapper constructor [dan25082001] arch-x86: Add instructions from SSE4.1 set. [rogerycchang] arch-riscv: Add new misa bit union ------------------------------------------ [...truncated 293.71 KB...] [SO Param] m5.objects.Uart, SimpleUart -> ALL/python/_m5/param_SimpleUart.cc [SO Param] m5.objects.Uart, Uart8250 -> ALL/python/_m5/param_Uart8250.cc [SO Param] m5.objects.Uart, SimpleUart -> ALL/params/SimpleUart.hh [SO Param] m5.objects.Uart, Uart8250 -> ALL/params/Uart8250.hh [ CXX] ALL/python/_m5/param_SimpleUart.cc -> .o [ CXX] ALL/python/_m5/param_Uart8250.cc -> .o [ CXX] ALL/dev/serial/serial.cc -> .o [ CXX] ALL/dev/serial/simple.cc -> .o [ TRACING] -> ALL/debug/Terminal.hh [ TRACING] -> ALL/debug/TerminalVerbose.hh [ CXX] ALL/dev/serial/terminal.cc -> .o [ CXX] ALL/dev/serial/uart.cc -> .o [ CXX] ALL/dev/serial/uart8250.cc -> .o [ TRACING] -> ALL/debug/Terminal.cc [ CXX] ALL/debug/Terminal.cc -> .o [ TRACING] -> ALL/debug/TerminalVerbose.cc [ CXX] ALL/debug/TerminalVerbose.cc -> .o [ TRACING] -> ALL/debug/Uart.cc [ CXX] ALL/debug/Uart.cc -> .o [ CXX] ALL/dev/i2c/I2C.py.cc -> .o [SO Param] m5.objects.I2C, I2CDevice -> ALL/python/_m5/param_I2CDevice.cc [SO Param] m5.objects.I2C, I2CBus -> ALL/python/_m5/param_I2CBus.cc [SO Param] m5.objects.I2C, I2CDevice -> ALL/params/I2CDevice.hh [SO Param] m5.objects.I2C, I2CBus -> ALL/params/I2CBus.hh [ CXX] ALL/python/_m5/param_I2CDevice.cc -> .o [ CXX] ALL/python/_m5/param_I2CBus.cc -> .o [ CXX] ALL/dev/i2c/bus.cc -> .o [ CXX] ALL/dev/pci/PciDevice.py.cc -> .o [SO Param] m5.objects.PciDevice, PciBar -> ALL/python/_m5/param_PciBar.cc [SO Param] m5.objects.PciDevice, PciBarNone -> ALL/python/_m5/param_PciBarNone.cc [ CXX] ALL/python/_m5/param_PciBar.cc -> .o [ CXX] ALL/python/_m5/param_PciBarNone.cc -> .o [SO Param] m5.objects.PciDevice, PciIoBar -> ALL/python/_m5/param_PciIoBar.cc [ CXX] ALL/python/_m5/param_PciIoBar.cc -> .o [SO Param] m5.objects.PciDevice, PciLegacyIoBar -> ALL/python/_m5/param_PciLegacyIoBar.cc [ CXX] ALL/python/_m5/param_PciLegacyIoBar.cc -> .o [SO Param] m5.objects.PciDevice, PciMemBar -> ALL/python/_m5/param_PciMemBar.cc [ CXX] ALL/python/_m5/param_PciMemBar.cc -> .o [SO Param] m5.objects.PciDevice, PciMemUpperBar -> ALL/python/_m5/param_PciMemUpperBar.cc [ CXX] ALL/python/_m5/param_PciMemUpperBar.cc -> .o [SO Param] m5.objects.PciDevice, PciDevice -> ALL/python/_m5/param_PciDevice.cc [ CXX] ALL/python/_m5/param_PciDevice.cc -> .o [ TRACING] -> ALL/debug/PciDevice.hh [ CXX] ALL/dev/pci/device.cc -> .o [ TRACING] -> ALL/debug/PciDevice.cc [ CXX] ALL/debug/PciDevice.cc -> .o [ CXX] ALL/dev/pci/PciHost.py.cc -> .o [SO Param] m5.objects.PciHost, PciHost -> ALL/python/_m5/param_PciHost.cc [ CXX] ALL/python/_m5/param_PciHost.cc -> .o [SO Param] m5.objects.PciHost, GenericPciHost -> ALL/python/_m5/param_GenericPciHost.cc [ CXX] ALL/python/_m5/param_GenericPciHost.cc -> .o [ TRACING] -> ALL/debug/PciHost.hh [ CXX] ALL/dev/pci/host.cc -> .o [ TRACING] -> ALL/debug/PciHost.cc [ CXX] ALL/debug/PciHost.cc -> .o [ CXX] ALL/dev/pci/CopyEngine.py.cc -> .o [SO Param] m5.objects.CopyEngine, CopyEngine -> ALL/python/_m5/param_CopyEngine.cc [SO Param] m5.objects.CopyEngine, CopyEngine -> ALL/params/CopyEngine.hh [ CXX] ALL/python/_m5/param_CopyEngine.cc -> .o [ TRACING] -> ALL/debug/DMACopyEngine.hh [ CXX] ALL/dev/pci/copy_engine.cc -> .o [ TRACING] -> ALL/debug/DMACopyEngine.cc [ CXX] ALL/debug/DMACopyEngine.cc -> .o [ CXX] ALL/dev/lupio/LupioBLK.py.cc -> .o [SO Param] m5.objects.LupioBLK, LupioBLK -> ALL/python/_m5/param_LupioBLK.cc [SO Param] m5.objects.LupioBLK, LupioBLK -> ALL/params/LupioBLK.hh [ TRACING] -> ALL/debug/LupioBLK.hh [ CXX] ALL/dev/lupio/LupioIPI.py.cc -> .o [ CXX] ALL/python/_m5/param_LupioBLK.cc -> .o [SO Param] m5.objects.LupioIPI, LupioIPI -> ALL/python/_m5/param_LupioIPI.cc [ CXX] ALL/dev/lupio/LupioPIC.py.cc -> .o [SO Param] m5.objects.LupioPIC, LupioPIC -> ALL/python/_m5/param_LupioPIC.cc [SO Param] m5.objects.LupioIPI, LupioIPI -> ALL/params/LupioIPI.hh [ CXX] ALL/python/_m5/param_LupioPIC.cc -> .o [ CXX] ALL/python/_m5/param_LupioIPI.cc -> .o [ CXX] ALL/dev/lupio/LupioRNG.py.cc -> .o [SO Param] m5.objects.LupioRNG, LupioRNG -> ALL/python/_m5/param_LupioRNG.cc [SO Param] m5.objects.LupioRNG, LupioRNG -> ALL/params/LupioRNG.hh [ TRACING] -> ALL/debug/LupioRNG.hh [ CXX] ALL/dev/lupio/LupioRTC.py.cc -> .o [ CXX] ALL/python/_m5/param_LupioRNG.cc -> .o [SO Param] m5.objects.LupioRTC, LupioRTC -> ALL/python/_m5/param_LupioRTC.cc [SO Param] m5.objects.LupioRTC, LupioRTC -> ALL/params/LupioRTC.hh [ TRACING] -> ALL/debug/LupioRTC.hh [ CXX] ALL/python/_m5/param_LupioRTC.cc -> .o [ CXX] ALL/dev/lupio/LupioTMR.py.cc -> .o [SO Param] m5.objects.LupioTMR, LupioTMR -> ALL/python/_m5/param_LupioTMR.cc [ CXX] ALL/dev/lupio/LupioTTY.py.cc -> .o [SO Param] m5.objects.LupioTTY, LupioTTY -> ALL/python/_m5/param_LupioTTY.cc [SO Param] m5.objects.LupioTMR, LupioTMR -> ALL/params/LupioTMR.hh [ CXX] ALL/dev/lupio/LupioSYS.py.cc -> .o [SO Param] m5.objects.LupioTTY, LupioTTY -> ALL/params/LupioTTY.hh [ CXX] ALL/python/_m5/param_LupioTMR.cc -> .o [ CXX] ALL/python/_m5/param_LupioTTY.cc -> .o [SO Param] m5.objects.LupioSYS, LupioSYS -> ALL/python/_m5/param_LupioSYS.cc [ TRACING] -> ALL/debug/LupioBLK.cc [SO Param] m5.objects.LupioSYS, LupioSYS -> ALL/params/LupioSYS.hh [ CXX] ALL/debug/LupioBLK.cc -> .o [ TRACING] -> ALL/debug/LupioSYS.hh [ TRACING] -> ALL/debug/LupioIPI.cc [ CXX] ALL/python/_m5/param_LupioSYS.cc -> .o [ TRACING] -> ALL/debug/LupioPIC.cc [ TRACING] -> ALL/debug/LupioIPI.hh [ TRACING] -> ALL/debug/LupioPIC.hh [ CXX] ALL/debug/LupioIPI.cc -> .o [ CXX] ALL/debug/LupioPIC.cc -> .o [ TRACING] -> ALL/debug/LupioRNG.cc [ TRACING] -> ALL/debug/LupioRTC.cc [ CXX] ALL/debug/LupioRNG.cc -> .o [ CXX] ALL/debug/LupioRTC.cc -> .o [ TRACING] -> ALL/debug/LupioTMR.cc [ TRACING] -> ALL/debug/LupioTTY.cc [ TRACING] -> ALL/debug/LupioTMR.hh [ TRACING] -> ALL/debug/LupioTTY.hh [ CXX] ALL/debug/LupioTMR.cc -> .o [ CXX] ALL/debug/LupioTTY.cc -> .o [ TRACING] -> ALL/debug/LupioSYS.cc [ CXX] ALL/dev/lupio/lupio_blk.cc -> .o [ CXX] ALL/debug/LupioSYS.cc -> .o [ CXX] ALL/dev/lupio/lupio_ipi.cc -> .o [ CXX] ALL/dev/lupio/lupio_pic.cc -> .o [ CXX] ALL/dev/lupio/lupio_rng.cc -> .o [ CXX] ALL/dev/lupio/lupio_rtc.cc -> .o [ CXX] ALL/dev/lupio/lupio_tmr.cc -> .o [ CXX] ALL/dev/lupio/lupio_tty.cc -> .o [ CXX] ALL/dev/lupio/lupio_sys.cc -> .o [ CXX] ALL/dev/x86/Pc.py.cc -> .o [SO Param] m5.objects.Pc, Pc -> ALL/python/_m5/param_Pc.cc [ CXX] ALL/python/_m5/param_Pc.cc -> .o [ CXX] ALL/dev/x86/pc.cc -> .o [ CXX] ALL/dev/x86/SouthBridge.py.cc -> .o [SO Param] m5.objects.SouthBridge, SouthBridge -> ALL/python/_m5/param_SouthBridge.cc [ CXX] ALL/python/_m5/param_SouthBridge.cc -> .o [ CXX] ALL/dev/x86/south_bridge.cc -> .o [ CXX] ALL/dev/x86/Cmos.py.cc -> .o [SO Param] m5.objects.Cmos, Cmos -> ALL/python/_m5/param_Cmos.cc [ CXX] ALL/python/_m5/param_Cmos.cc -> .o [ TRACING] -> ALL/debug/CMOS.hh [ CXX] ALL/dev/x86/cmos.cc -> .o [ TRACING] -> ALL/debug/CMOS.cc [ CXX] ALL/debug/CMOS.cc -> .o [ CXX] ALL/dev/x86/I8259.py.cc -> .o [SO Param] m5.objects.I8259, I8259 -> ALL/python/_m5/param_I8259.cc [ CXX] ALL/python/_m5/param_I8259.cc -> .o [ENUM STR] m5.objects.I8259, X86I8259CascadeMode -> ALL/enums/X86I8259CascadeMode.cc [ CXX] ALL/enums/X86I8259CascadeMode.cc -> .o [ TRACING] -> ALL/debug/I8259.hh [ CXX] ALL/dev/x86/i8259.cc -> .o [ TRACING] -> ALL/debug/I8259.cc [ CXX] ALL/debug/I8259.cc -> .o [ CXX] ALL/dev/x86/I8254.py.cc -> .o [SO Param] m5.objects.I8254, I8254 -> ALL/python/_m5/param_I8254.cc [ CXX] ALL/python/_m5/param_I8254.cc -> .o [ TRACING] -> ALL/debug/I8254.hh [ CXX] ALL/dev/x86/i8254.cc -> .o [ TRACING] -> ALL/debug/I8254.cc [ CXX] ALL/debug/I8254.cc -> .o [ CXX] ALL/dev/x86/I8237.py.cc -> .o [SO Param] m5.objects.I8237, I8237 -> ALL/python/_m5/param_I8237.cc [ CXX] ALL/dev/x86/i8237.cc -> .o [ CXX] ALL/python/_m5/param_I8237.cc -> .o [ TRACING] -> ALL/debug/I8237.cc [ TRACING] -> ALL/debug/I8237.hh [ CXX] ALL/debug/I8237.cc -> .o [ CXX] ALL/dev/x86/I8042.py.cc -> .o [SO Param] m5.objects.I8042, I8042 -> ALL/python/_m5/param_I8042.cc [ CXX] ALL/python/_m5/param_I8042.cc -> .o [ TRACING] -> ALL/debug/I8042.hh [ CXX] ALL/dev/x86/i8042.cc -> .o [ TRACING] -> ALL/debug/I8042.cc [ CXX] ALL/debug/I8042.cc -> .o [ CXX] ALL/dev/x86/X86Ide.py.cc -> .o [SO Param] m5.objects.X86Ide, X86IdeController -> ALL/python/_m5/param_X86IdeController.cc [SO Param] m5.objects.X86Ide, X86IdeController -> ALL/params/X86IdeController.hh [ CXX] ALL/dev/x86/PcSpeaker.py.cc -> .o [SO Param] m5.objects.PcSpeaker, PcSpeaker -> ALL/python/_m5/param_PcSpeaker.cc [ CXX] ALL/python/_m5/param_X86IdeController.cc -> .o [ CXX] ALL/python/_m5/param_PcSpeaker.cc -> .o [ CXX] ALL/dev/x86/ide_ctrl.cc -> .o [ TRACING] -> ALL/debug/PcSpeaker.hh [ CXX] ALL/dev/x86/speaker.cc -> .o [ TRACING] -> ALL/debug/PcSpeaker.cc [ CXX] ALL/debug/PcSpeaker.cc -> .o [ CXX] ALL/dev/x86/I82094AA.py.cc -> .o [SO Param] m5.objects.I82094AA, I82094AA -> ALL/python/_m5/param_I82094AA.cc [ CXX] ALL/python/_m5/param_I82094AA.cc -> .o [ TRACING] -> ALL/debug/I82094AA.hh [ CXX] ALL/dev/x86/i82094aa.cc -> .o [ TRACING] -> ALL/debug/I82094AA.cc [ CXX] ALL/debug/I82094AA.cc -> .o [ CXX] ALL/dev/x86/X86QemuFwCfg.py.cc -> .o [SO Param] m5.objects.X86QemuFwCfg, QemuFwCfgItemE820 -> ALL/python/_m5/param_QemuFwCfgItemE820.cc [SO Param] m5.objects.X86QemuFwCfg, QemuFwCfgItemE820 -> ALL/params/QemuFwCfgItemE820.hh [ CXX] ALL/python/_m5/param_QemuFwCfgItemE820.cc -> .o [ CXX] ALL/dev/x86/qemu_fw_cfg.cc -> .o [ CXX] ALL/dev/virtio/VirtIO.py.cc -> .o [SO Param] m5.objects.VirtIO, VirtIODeviceBase -> ALL/python/_m5/param_VirtIODeviceBase.cc [ CXX] ALL/python/_m5/param_VirtIODeviceBase.cc -> .o [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> ALL/python/_m5/param_VirtIODummyDevice.cc [SO Param] m5.objects.VirtIO, PciVirtIO -> ALL/python/_m5/param_PciVirtIO.cc [SO Param] m5.objects.VirtIO, VirtIODummyDevice -> ALL/params/VirtIODummyDevice.hh [SO Param] m5.objects.VirtIO, PciVirtIO -> ALL/params/PciVirtIO.hh [ CXX] ALL/python/_m5/param_VirtIODummyDevice.cc -> .o [ CXX] ALL/python/_m5/param_PciVirtIO.cc -> .o [ CXX] ALL/dev/virtio/VirtIOConsole.py.cc -> .o [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> ALL/python/_m5/param_VirtIOConsole.cc [SO Param] m5.objects.VirtIOConsole, VirtIOConsole -> ALL/params/VirtIOConsole.hh [ CXX] ALL/python/_m5/param_VirtIOConsole.cc -> .o [ CXX] ALL/dev/virtio/VirtIOBlock.py.cc -> .o [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> ALL/python/_m5/param_VirtIOBlock.cc [SO Param] m5.objects.VirtIOBlock, VirtIOBlock -> ALL/params/VirtIOBlock.hh [ CXX] ALL/dev/virtio/VirtIORng.py.cc -> .o [SO Param] m5.objects.VirtIORng, VirtIORng -> ALL/python/_m5/param_VirtIORng.cc [ CXX] ALL/python/_m5/param_VirtIOBlock.cc -> .o [SO Param] m5.objects.VirtIORng, VirtIORng -> ALL/params/VirtIORng.hh [ CXX] ALL/python/_m5/param_VirtIORng.cc -> .o [ CXX] ALL/dev/virtio/VirtIO9P.py.cc -> .o [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> ALL/python/_m5/param_VirtIO9PBase.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PBase -> ALL/params/VirtIO9PBase.hh [ CXX] ALL/python/_m5/param_VirtIO9PBase.cc -> .o [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> ALL/python/_m5/param_VirtIO9PProxy.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PProxy -> ALL/params/VirtIO9PProxy.hh [ CXX] ALL/python/_m5/param_VirtIO9PProxy.cc -> .o [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> ALL/python/_m5/param_VirtIO9PDiod.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PDiod -> ALL/params/VirtIO9PDiod.hh [ CXX] ALL/python/_m5/param_VirtIO9PDiod.cc -> .o [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> ALL/python/_m5/param_VirtIO9PSocket.cc [SO Param] m5.objects.VirtIO9P, VirtIO9PSocket -> ALL/params/VirtIO9PSocket.hh [ TRACING] -> ALL/debug/VIO.hh [ CXX] ALL/dev/virtio/base.cc -> .o [ CXX] ALL/python/_m5/param_VirtIO9PSocket.cc -> .o [ CXX] ALL/dev/virtio/pci.cc -> .o [ TRACING] -> ALL/debug/VIOConsole.hh [ CXX] ALL/dev/virtio/console.cc -> .o [ TRACING] -> ALL/debug/VIOBlock.hh [ CXX] ALL/dev/virtio/block.cc -> .o [ TRACING] -> ALL/debug/VIO9P.hh [ TRACING] -> ALL/debug/VIO9PData.hh [ CXX] ALL/dev/virtio/fs9p.cc -> .o [ TRACING] -> ALL/debug/VIORng.hh [ CXX] ALL/dev/virtio/rng.cc -> .o [ TRACING] -> ALL/debug/VIO.cc [ CXX] ALL/debug/VIO.cc -> .o [ TRACING] -> ALL/debug/VIORng.cc [ CXX] ALL/debug/VIORng.cc -> .o Build timed out (after 8,640 minutes). Marking the build as failed. Terminated Build was aborted Archiving artifacts _______________________________________________ gem5-dev mailing list -- gem5-dev@gem5.org To unsubscribe send an email to gem5-dev-le...@gem5.org
