Richard Cooper has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/69680?usp=email )
Change subject: arch-arm: Fix formatting of v8 Tarmac Register records
......................................................................
arch-arm: Fix formatting of v8 Tarmac Register records
The Tarmac v8 Register ("R") record serialisation formats the
underlying 64-bit storage using a format string field width specifier.
This sets a minimum number of hex characters for the value, rather
than a maximum number of characters.
Because of this, when formatting a narrowed view of a larger
register (e.g. the 32-bit w0 view of the 64-bit x0 register), if any
of the upper bits in the underlying storage are set, then the number
of hex characters used will be the minimum number required to
represent the full value. This could result in irregular formatting,
for example an odd number of hex characters.
This irregular formatting can cause parsing warnings or failures in
some Tarmac tools, for example the Arm Tarmac Trace Utilities [1].
This patch modifies the "R" record formatting to first mask off the
upper bits of the value in the underlying storage to ensure that the
correct number of hex characters are used for the size of the register
being serialised.
[1] https://github.com/ARM-software/tarmac-trace-utilities
Change-Id: Idbd80553d3bcdb56fa9edddd48440ab7d4dff073
---
M src/arch/arm/tracers/tarmac_record_v8.cc
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc
b/src/arch/arm/tracers/tarmac_record_v8.cc
index 29606c3..a3850b3 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2017-2019 ARM Limited
+ * Copyright (c) 2017-2019, 2022 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -293,8 +293,9 @@
TarmacTracerRecordV8::TraceRegEntryV8::formatReg() const
{
if (regWidth <= 64) {
- // Register width is < 64 bit (scalar register).
- return csprintf("%0*x", regWidth / 4, values[Lo]);
+ // Register width is <= 64 bit (scalar register).
+ const auto regValue = values[Lo] & mask(regWidth);
+ return csprintf("%0*x", regWidth / 4, regValue);
} else {
// Register width is > 64 bit (vector). Iterate over every vector
--
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Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Idbd80553d3bcdb56fa9edddd48440ab7d4dff073
Gerrit-Change-Number: 69680
Gerrit-PatchSet: 1
Gerrit-Owner: Richard Cooper <richard.coo...@arm.com>
Gerrit-MessageType: newchange
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