Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70558?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Move RO values from ISA::read to the reset field
......................................................................
arch-arm: Move RO values from ISA::read to the reset field
This is simplyfying the ISA::readMiscReg, and it is stopping
us from recomputing values that won't change throughout the
simulation
Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70558
Tested-by: kokoro <noreply+kok...@google.com>
Maintainer: Jason Lowe-Power <power...@gmail.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 49 insertions(+), 66 deletions(-)
Approvals:
Jason Lowe-Power: Looks good to me, approved
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index f55235d..14349b1 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -486,35 +486,6 @@
warn_once("The ccsidr register isn't implemented and "
"always reads as 0.\n");
break;
- case MISCREG_CTR: // AArch32, ARMv7, top bit set
- case MISCREG_CTR_EL0: // AArch64
- {
- //all caches have the same line size in gem5
- //4 byte words in ARM
- unsigned lineSizeWords =
- tc->getSystemPtr()->cacheLineSize() / 4;
- unsigned log2LineSizeWords = 0;
-
- while (lineSizeWords >>= 1) {
- ++log2LineSizeWords;
- }
-
- CTR ctr = 0;
- //log2 of minimun i-cache line size (words)
- ctr.iCacheLineSize = log2LineSizeWords;
- //b11 - gem5 uses pipt
- ctr.l1IndexPolicy = 0x3;
- //log2 of minimum d-cache line size (words)
- ctr.dCacheLineSize = log2LineSizeWords;
- //log2 of max reservation size (words)
- ctr.erg = log2LineSizeWords;
- //log2 of max writeback size (words)
- ctr.cwg = log2LineSizeWords;
- //b100 - gem5 format is ARMv7
- ctr.format = 0x4;
-
- return ctr;
- }
case MISCREG_ACTLR:
warn("Not doing anything for miscreg ACTLR\n");
break;
@@ -615,11 +586,6 @@
l2ctlr.numCPUs = tc->getSystemPtr()->threads.size() - 1;
return l2ctlr;
}
- case MISCREG_DBGDIDR:
- /* For now just implement the version number.
- * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
- */
- return 0x5 << 16;
case MISCREG_DBGDSCRint:
return readMiscRegNoEffect(MISCREG_DBGDSCRint);
case MISCREG_ISR:
@@ -632,8 +598,6 @@
readMiscRegNoEffect(MISCREG_CPSR),
readMiscRegNoEffect(MISCREG_SCR_EL3));
}
- case MISCREG_DCZID_EL0:
- return 0x04; // DC ZVA clear 64-byte chunks
case MISCREG_HCPTR:
{
RegVal val = readMiscRegNoEffect(idx);
@@ -656,36 +620,6 @@
case MISCREG_HIFAR: // alias for secure IFAR
return readMiscRegNoEffect(MISCREG_IFAR_S);
- case MISCREG_ID_PFR0:
- // !ThumbEE | !Jazelle | Thumb | ARM
- return 0x00000031;
- case MISCREG_ID_PFR1:
- { // Timer | Virti | !M Profile | TrustZone | ARMv4
- bool have_timer = (system->getGenericTimer() != nullptr);
- return 0x00000001 |
- (release->has(ArmExtension::SECURITY) ?
- 0x00000010 : 0x0) |
- (release->has(ArmExtension::VIRTUALIZATION) ?
- 0x00001000 : 0x0) |
- (have_timer ? 0x00010000 : 0x0);
- }
- case MISCREG_ID_AA64PFR0_EL1:
- return 0x0000000000000002 | // AArch{64,32} supported at EL0
- 0x0000000000000020 | // EL1
- (release->has(ArmExtension::VIRTUALIZATION) ?
- 0x0000000000000200 : 0) | // EL2
- (release->has(ArmExtension::SECURITY) ?
- 0x0000000000002000 : 0) | // EL3
- (release->has(ArmExtension::FEAT_SVE) ?
- 0x0000000100000000 : 0) | // SVE
- (release->has(ArmExtension::FEAT_SEL2) ?
- 0x0000001000000000 : 0) | // SecEL2
- (gicv3CpuInterface ? 0x0000000001000000 : 0);
- case MISCREG_ID_AA64PFR1_EL1:
- return 0x0 |
- (release->has(ArmExtension::FEAT_SME) ?
- 0x1 << 24 : 0); // SME
-
// Generic Timer registers
case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 7a06da1..960c2be 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2273,6 +2273,10 @@
// AArch32 CP14 registers
InitReg(MISCREG_DBGDIDR)
+ /* For now just implement the version number.
+ * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
+ */
+ .reset(0x5 << 16)
.allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
InitReg(MISCREG_DBGDSCRint)
.allPrivileges().monSecureWrite(0).monNonSecureWrite(0);
@@ -2514,6 +2518,34 @@
.reset(midr)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CTR)
+ .reset([system=p.system](){
+ //all caches have the same line size in gem5
+ //4 byte words in ARM
+ unsigned line_size_words =
+ system->cacheLineSize() / 4;
+ unsigned log2_line_size_words = 0;
+
+ while (line_size_words >>= 1) {
+ ++log2_line_size_words;
+ }
+
+ CTR ctr = 0;
+ //log2 of minimun i-cache line size (words)
+ ctr.iCacheLineSize = log2_line_size_words;
+ //b11 - gem5 uses pipt
+ ctr.l1IndexPolicy = 0x3;
+ //log2 of minimum d-cache line size (words)
+ ctr.dCacheLineSize = log2_line_size_words;
+ //log2 of max reservation size (words)
+ ctr.erg = log2_line_size_words;
+ //log2 of max writeback size (words)
+ ctr.cwg = log2_line_size_words;
+ //b100 - gem5 format is ARMv7
+ ctr.format = 0x4;
+
+ return ctr;
+ }())
+ .unserialize(0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TCMTR)
.allPrivileges().exceptUserMode().writes(0);
@@ -2528,8 +2560,20 @@
.warnNotFail()
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_PFR0)
+ .reset(0x00000031) // !ThumbEE | !Jazelle | Thumb | ARM
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_PFR1)
+ .reset([release=release,system=system](){
+ // Timer | Virti | !M Profile | TrustZone | ARMv4
+ bool have_timer = (system && system->getGenericTimer() !=
nullptr);
+ return 0x00000001 |
+ (release->has(ArmExtension::SECURITY) ?
+ 0x00000010 : 0x0) |
+ (release->has(ArmExtension::VIRTUALIZATION) ?
+ 0x00001000 : 0x0) |
+ (have_timer ? 0x00010000 : 0x0);
+ }())
+ .unserialize(0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_DFR0)
.reset(p.pmu ? 0x03000000 : 0)
@@ -3772,9 +3816,13 @@
pfr0_el1.gic = FullSystem && getGICv3CPUInterface(tc) ? 0x1 : 0;
return pfr0_el1;
}())
+ .unserialize(0)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64PFR1_EL1)
+ .reset(release->has(ArmExtension::FEAT_SME) ?
+ 0x1 << 24 : 0)
+ .unserialize(0)
.faultRead(EL1, HCR_TRAP(tid3))
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_ID_AA64DFR0_EL1)
@@ -3919,6 +3967,7 @@
.reads(1)
.mapsTo(MISCREG_CTR);
InitReg(MISCREG_DCZID_EL0)
+ .reset(0x04) // DC ZVA clear 64-byte chunks
.reads(1);
InitReg(MISCREG_VPIDR_EL2)
.hyp().mon()
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Gerrit-Change-Number: 70558
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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