Giacomo Travaglini has submitted this change. (
https://gem5-review.googlesource.com/c/public/gem5/+/70560?usp=email )
(
1 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the
submitted one.
)Change subject: arch-arm: Implement RAZ/WI with raz specifier
......................................................................
arch-arm: Implement RAZ/WI with raz specifier
Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini <giacomo.travagl...@arm.com>
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560
Maintainer: Jason Lowe-Power <power...@gmail.com>
Tested-by: kokoro <noreply+kok...@google.com>
---
M src/arch/arm/isa.cc
M src/arch/arm/regs/misc.cc
2 files changed, 5 insertions(+), 6 deletions(-)
Approvals:
Richard Cooper: Looks good to me, approved
kokoro: Regressions pass
Jason Lowe-Power: Looks good to me, approved
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 14349b1..7df8978 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -470,12 +470,6 @@
return readMiscRegNoEffect(idx);
}
break;
- case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
- case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
- case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
- case MISCREG_AIDR: // AUX ID set to 0
- case MISCREG_TCMTR: // No TCM's
- return 0;
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 960c2be..6c5a9dd 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2505,12 +2505,15 @@
.unimplemented()
.allPrivileges();
InitReg(MISCREG_JIDR)
+ .raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
InitReg(MISCREG_TEEHBR)
.allPrivileges();
InitReg(MISCREG_JOSCR)
+ .raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
InitReg(MISCREG_JMCR)
+ .raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
// AArch32 CP15 registers
@@ -2548,6 +2551,7 @@
.unserialize(0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TCMTR)
+ .raz() // No TCM's
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TLBTR)
.reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@
InitReg(MISCREG_CLIDR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_AIDR)
+ .raz() // AUX ID set to 0
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CSSELR)
.banked();
--
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Gerrit-MessageType: merged
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Gerrit-Change-Number: 70560
Gerrit-PatchSet: 3
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Andreas Sandberg <andreas.sandb...@arm.com>
Gerrit-Reviewer: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Jason Lowe-Power <power...@gmail.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Reviewer: kokoro <noreply+kok...@google.com>
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