Attention is currently required from: Richard Cooper.
Hello Richard Cooper,
I'd like you to do a code review.
Please visit
https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email
to review the following change.
Change subject: arch-arm, cpu, configs: Add new Op Classes for Matrix
Multiply insts
......................................................................
arch-arm, cpu, configs: Add new Op Classes for Matrix Multiply insts
Add SimdMatMultAcc and SimdFloatMatMultAcc Op Classes for the SVE
Matrix Multiply Accumulate instructions in the SVE F32MM, F64MM and
I8MM extensions.
Initial latencies have been set to be the same as SimdMultAcc and
SimdFloatMultAcc respectively.
Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Reviewed-by: Richard Cooper <richard.coo...@arm.com>
---
M configs/common/cores/arm/HPI.py
M configs/common/cores/arm/O3_ARM_v7a.py
M configs/common/cores/arm/ex5_LITTLE.py
M configs/common/cores/arm/ex5_big.py
M src/arch/arm/isa/insts/sve.isa
M src/cpu/FuncUnit.py
M src/cpu/minor/BaseMinorCPU.py
M src/cpu/o3/FuncUnitConfig.py
M src/cpu/op_class.hh
9 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/configs/common/cores/arm/HPI.py
b/configs/common/cores/arm/HPI.py
index c7a8127..d3d4605 100644
--- a/configs/common/cores/arm/HPI.py
+++ b/configs/common/cores/arm/HPI.py
@@ -1420,6 +1420,7 @@
"SimdMisc",
"SimdMult",
"SimdMultAcc",
+ "SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdSqrt",
@@ -1431,6 +1432,7 @@
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
+ "SimdFloatMatMultAcc",
"SimdFloatSqrt",
]
)
diff --git a/configs/common/cores/arm/O3_ARM_v7a.py
b/configs/common/cores/arm/O3_ARM_v7a.py
index 77dc4e4..be9abd6 100644
--- a/configs/common/cores/arm/O3_ARM_v7a.py
+++ b/configs/common/cores/arm/O3_ARM_v7a.py
@@ -53,6 +53,7 @@
OpDesc(opClass="SimdMisc", opLat=3),
OpDesc(opClass="SimdMult", opLat=5),
OpDesc(opClass="SimdMultAcc", opLat=5),
+ OpDesc(opClass='SimdMatMultAcc',opLat=5),
OpDesc(opClass="SimdShift", opLat=3),
OpDesc(opClass="SimdShiftAcc", opLat=3),
OpDesc(opClass="SimdSqrt", opLat=9),
@@ -64,6 +65,7 @@
OpDesc(opClass="SimdFloatMisc", opLat=3),
OpDesc(opClass="SimdFloatMult", opLat=3),
OpDesc(opClass="SimdFloatMultAcc", opLat=5),
+ OpDesc(opClass='SimdFloatMatMultAcc',opLat=5),
OpDesc(opClass="SimdFloatSqrt", opLat=9),
OpDesc(opClass="FloatAdd", opLat=5),
OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/configs/common/cores/arm/ex5_LITTLE.py
b/configs/common/cores/arm/ex5_LITTLE.py
index 6974837..b6fed94 100644
--- a/configs/common/cores/arm/ex5_LITTLE.py
+++ b/configs/common/cores/arm/ex5_LITTLE.py
@@ -56,6 +56,7 @@
OpDesc(opClass="SimdMisc", opLat=3),
OpDesc(opClass="SimdMult", opLat=4),
OpDesc(opClass="SimdMultAcc", opLat=5),
+ OpDesc(opClass='SimdMatMultAcc',opLat=5),
OpDesc(opClass="SimdShift", opLat=3),
OpDesc(opClass="SimdShiftAcc", opLat=3),
OpDesc(opClass="SimdSqrt", opLat=9),
@@ -67,6 +68,7 @@
OpDesc(opClass="SimdFloatMisc", opLat=6),
OpDesc(opClass="SimdFloatMult", opLat=15),
OpDesc(opClass="SimdFloatMultAcc", opLat=6),
+ OpDesc(opClass='SimdFloatMatMultAcc',opLat=6),
OpDesc(opClass="SimdFloatSqrt", opLat=17),
OpDesc(opClass="FloatAdd", opLat=8),
OpDesc(opClass="FloatCmp", opLat=6),
diff --git a/configs/common/cores/arm/ex5_big.py
b/configs/common/cores/arm/ex5_big.py
index 70af6b8..4383f96 100644
--- a/configs/common/cores/arm/ex5_big.py
+++ b/configs/common/cores/arm/ex5_big.py
@@ -58,6 +58,7 @@
OpDesc(opClass="SimdMisc", opLat=3),
OpDesc(opClass="SimdMult", opLat=6),
OpDesc(opClass="SimdMultAcc", opLat=5),
+ OpDesc(opClass='SimdMatMultAcc',opLat=5),
OpDesc(opClass="SimdShift", opLat=3),
OpDesc(opClass="SimdShiftAcc", opLat=3),
OpDesc(opClass="SimdSqrt", opLat=9),
@@ -69,6 +70,7 @@
OpDesc(opClass="SimdFloatMisc", opLat=3),
OpDesc(opClass="SimdFloatMult", opLat=6),
OpDesc(opClass="SimdFloatMultAcc", opLat=1),
+ OpDesc(opClass='SimdFloatMatMultAcc',opLat=1),
OpDesc(opClass="SimdFloatSqrt", opLat=9),
OpDesc(opClass="FloatAdd", opLat=6),
OpDesc(opClass="FloatCmp", opLat=5),
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index b6b560d..0993c47 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -3929,7 +3929,7 @@
fplibMul<DestElement>(srcElemA, srcElemB, fpscr), fpscr);
'''
# FMMLA (vectors)
- sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMultAccOp', floatTypes,
+ sveMatMulInst('fmmla', 'Fmmla', 'SimdFloatMatMultAccOp', floatTypes,
numDestRows=2, numDestCols=2, K=2,
elt_mul_op=fmmlaCode)
@@ -4208,17 +4208,17 @@
mmlaCode = ('destElem += srcElemA * srcElemB')
# SMMLA (vectors)
- sveMatMulInst('smmla', 'Smmla', 'SimdMultAccOp',
+ sveMatMulInst('smmla', 'Smmla', 'SimdMatMultAccOp',
(('int32_t', 'int8_t', 'int8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)
# USMMLA (vectors)
- sveMatMulInst('usmmla', 'Usmmla', 'SimdMultAccOp',
+ sveMatMulInst('usmmla', 'Usmmla', 'SimdMatMultAccOp',
(('int32_t', 'uint8_t', 'int8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)
# UMMLA (vectors)
- sveMatMulInst('ummla', 'Ummla', 'SimdMultAccOp',
+ sveMatMulInst('ummla', 'Ummla', 'SimdMatMultAccOp',
(('uint32_t', 'uint8_t', 'uint8_t'),),
numDestRows=2, numDestCols=2, K=8,
elt_mul_op=mmlaCode)
diff --git a/src/cpu/FuncUnit.py b/src/cpu/FuncUnit.py
index a1050de..012dfd0 100644
--- a/src/cpu/FuncUnit.py
+++ b/src/cpu/FuncUnit.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010, 2017-2018, 2022 ARM Limited
+# Copyright (c) 2010, 2017-2018, 2020, 2022 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -62,6 +62,7 @@
"SimdMisc",
"SimdMult",
"SimdMultAcc",
+ "SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdDiv",
@@ -74,6 +75,7 @@
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
+ "SimdFloatMatMultAcc",
"SimdFloatSqrt",
"SimdReduceAdd",
"SimdReduceAlu",
diff --git a/src/cpu/minor/BaseMinorCPU.py b/src/cpu/minor/BaseMinorCPU.py
index 6641a39..bd27b92 100644
--- a/src/cpu/minor/BaseMinorCPU.py
+++ b/src/cpu/minor/BaseMinorCPU.py
@@ -189,6 +189,7 @@
"SimdMisc",
"SimdMult",
"SimdMultAcc",
+ "SimdMatMultAcc",
"SimdShift",
"SimdShiftAcc",
"SimdDiv",
@@ -201,6 +202,7 @@
"SimdFloatMisc",
"SimdFloatMult",
"SimdFloatMultAcc",
+ "SimdFloatMatMultAcc",
"SimdFloatSqrt",
"SimdReduceAdd",
"SimdReduceAlu",
diff --git a/src/cpu/o3/FuncUnitConfig.py b/src/cpu/o3/FuncUnitConfig.py
index 3d626c2..7ba49c9 100644
--- a/src/cpu/o3/FuncUnitConfig.py
+++ b/src/cpu/o3/FuncUnitConfig.py
@@ -1,4 +1,4 @@
-# Copyright (c) 2010, 2017 ARM Limited
+# Copyright (c) 2010, 2017, 2020 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
@@ -87,6 +87,7 @@
OpDesc(opClass="SimdMisc"),
OpDesc(opClass="SimdMult"),
OpDesc(opClass="SimdMultAcc"),
+ OpDesc(opClass="SimdMatMultAcc"),
OpDesc(opClass="SimdShift"),
OpDesc(opClass="SimdShiftAcc"),
OpDesc(opClass="SimdDiv"),
@@ -99,6 +100,7 @@
OpDesc(opClass="SimdFloatMisc"),
OpDesc(opClass="SimdFloatMult"),
OpDesc(opClass="SimdFloatMultAcc"),
+ OpDesc(opClass="SimdFloatMatMultAcc"),
OpDesc(opClass="SimdFloatSqrt"),
OpDesc(opClass="SimdReduceAdd"),
OpDesc(opClass="SimdReduceAlu"),
diff --git a/src/cpu/op_class.hh b/src/cpu/op_class.hh
index 94d2794..0151df0 100644
--- a/src/cpu/op_class.hh
+++ b/src/cpu/op_class.hh
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010, 2017-2018, 2022 ARM Limited
+ * Copyright (c) 2010, 2017-2018, 2020, 2022 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -72,6 +72,7 @@
static const OpClass SimdMiscOp = enums::SimdMisc;
static const OpClass SimdMultOp = enums::SimdMult;
static const OpClass SimdMultAccOp = enums::SimdMultAcc;
+static const OpClass SimdMatMultAccOp = enums::SimdMatMultAcc;
static const OpClass SimdShiftOp = enums::SimdShift;
static const OpClass SimdShiftAccOp = enums::SimdShiftAcc;
static const OpClass SimdDivOp = enums::SimdDiv;
@@ -87,6 +88,7 @@
static const OpClass SimdFloatMiscOp = enums::SimdFloatMisc;
static const OpClass SimdFloatMultOp = enums::SimdFloatMult;
static const OpClass SimdFloatMultAccOp = enums::SimdFloatMultAcc;
+static const OpClass SimdFloatMatMultAccOp = enums::SimdFloatMatMultAcc;
static const OpClass SimdFloatSqrtOp = enums::SimdFloatSqrt;
static const OpClass SimdFloatReduceCmpOp = enums::SimdFloatReduceCmp;
static const OpClass SimdFloatReduceAddOp = enums::SimdFloatReduceAdd;
--
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https://gem5-review.googlesource.com/c/public/gem5/+/70734?usp=email
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: Ifab63a0efbb0ccfbd272245e0b0b055279f66e3a
Gerrit-Change-Number: 70734
Gerrit-PatchSet: 1
Gerrit-Owner: Giacomo Travaglini <giacomo.travagl...@arm.com>
Gerrit-Reviewer: Richard Cooper <richard.coo...@arm.com>
Gerrit-Attention: Richard Cooper <richard.coo...@arm.com>
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