See <https://jenkins.gem5.org/job/nightly/609/display/redirect?page=changes>
Changes:
[Giacomo Travaglini] arch-arm: Add UNSERIALIZE flag to address cpt compatibility
[Giacomo Travaglini] arch-arm: Move RO values from ISA::read to the reset field
[Giacomo Travaglini] arch-arm: Provide default mask for raz/rao helpers
[Giacomo Travaglini] arch-arm: Implement RAZ/WI with raz specifier
[Giacomo Travaglini] arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug
arch
[Giacomo Travaglini] arch-arm: Group self hosted debug writes in ISA switch
[Giacomo Travaglini] arch-arm: Implement RES0/RES1 with miscreg specifiers
[Giacomo Travaglini] arch-arm: Remove unnecessary case in ISA::readMiscReg
[Giacomo Travaglini] arch-arm: Simplify FPSCR writes
[Giacomo Travaglini] arch-arm: Extend SCTLR to be 64-bit wide
[Giacomo Travaglini] arch-arm: Implement FEAT_TLBIOS
[Bobby R. Bruce] arch-riscv: Fix WFI for O3 CPU
[alexrichardson] scons: default to not duplicating sources in the build
directory
[alexrichardson] tests: Add '--duplicate-sources' to libgem5 SST build
------------------------------------------
[...truncated 4.93 MB...]
[ SHCXX] ARM/cxx_config/HMCController.cc -> .os
[ SHCXX] ARM/cxx_config/MessageBuffer.cc -> .os
[ SHCXX] ARM/cxx_config/ArmSPI.cc -> .os
[ SHCXX] src/sim/clock_domain.cc -> ARM/sim/clock_domain.os
[ SHCXX] src/mem/ruby/network/garnet/OutVcState.cc ->
ARM/mem/ruby/network/garnet/OutVcState.os
[ SHCXX] src/cpu/simple/atomic.cc -> ARM/cpu/simple/atomic.os
[ SHCXX] src/mem/cache/mshr.cc -> ARM/mem/cache/mshr.os
[ SHCXX] src/mem/serial_link.cc -> ARM/mem/serial_link.os
[ SHCXX] ARM/cxx_config/System.cc -> .os
[ SHCXX] ARM/python/_m5/param_HMCController.cc -> .os
[ SHCXX] ARM/cxx_config/HDLcd.cc -> .os
[ SHCXX] ARM/python/_m5/param_QoSMemSinkInterface.cc -> .os
[ SHCXX] ARM/python/_m5/param_MessageBuffer.cc -> .os
[ SHCXX] src/mem/simple_mem.cc -> ARM/mem/simple_mem.os
[ SHCXX] ARM/python/_m5/param_ArmSPI.cc -> .os
[ SHCXX] src/mem/ruby/network/garnet/NetworkLink.cc ->
ARM/mem/ruby/network/garnet/NetworkLink.os
[ SHCXX] ARM/cxx_config/BaseAtomicSimpleCPU.cc -> .os
[ SHCXX] src/cpu/testers/memtest/memtest.cc ->
ARM/cpu/testers/memtest/memtest.os
[ SHCXX] src/dev/arm/gpu_nomali.cc -> ARM/dev/arm/gpu_nomali.os
[ SHCXX] ARM/python/_m5/param_HDLcd.cc -> .os
[ SHCXX] ARM/cxx_config/QoSMemSinkCtrl.cc -> .os
[ SHCXX] ARM/cxx_config/BasicRouter.cc -> .os
[ SHCXX] ARM/cxx_config/ArmInterruptPin.cc -> .os
[ SHCXX] src/arch/arm/pmu.cc -> ARM/arch/arm/pmu.os
[ SHCXX] src/dev/arm/css/scmi_protocols.cc ->
ARM/dev/arm/css/scmi_protocols.os
[ SHCXX] src/mem/ruby/network/garnet/NetworkInterface.cc ->
ARM/mem/ruby/network/garnet/NetworkInterface.os
[ SHCXX] ARM/python/_m5/param_BaseAtomicSimpleCPU.cc -> .os
[ SHCXX] src/mem/hmc_controller.cc -> ARM/mem/hmc_controller.os
[ SHCXX] src/cpu/o3/fetch.cc -> ARM/cpu/o3/fetch.os
[ SHCXX] ARM/cxx_config/MemTest.cc -> .os
[ SHCXX] src/dev/arm/watchdog_sp805.cc -> ARM/dev/arm/watchdog_sp805.os
[ SHCXX] ARM/cxx_config/VoltageDomain.cc -> .os
[ SHCXX] ARM/cxx_config/Pl111.cc -> .os
[ SHCXX] ARM/python/_m5/param_QoSMemSinkCtrl.cc -> .os
[ SHCXX] ARM/python/_m5/param_BasicRouter.cc -> .os
[ SHCXX] src/mem/physical.cc -> ARM/mem/physical.os
[ SHCXX] ARM/python/_m5/param_ArmInterruptPin.cc -> .os
[ SHCXX] src/dev/arm/css/scmi_platform.cc -> ARM/dev/arm/css/scmi_platform.os
[ SHCXX] src/sim/ticked_object.cc -> ARM/sim/ticked_object.os
[ SHCXX] ARM/cxx_config/ArmPMU.cc -> .os
[ SHCXX] src/mem/xbar.cc -> ARM/mem/xbar.os
[ SHCXX] src/cpu/o3/dyn_inst.cc -> ARM/cpu/o3/dyn_inst.os
[ SHCXX] ARM/python/_m5/param_MemTest.cc -> .os
[ SHCXX] src/dev/arm/watchdog_generic.cc -> ARM/dev/arm/watchdog_generic.os
[ SHCXX] ARM/python/_m5/param_VoltageDomain.cc -> .os
[ SHCXX] ARM/python/_m5/param_Pl111.cc -> .os
[ SHCXX] ARM/cxx_config/BaseGic.cc -> .os
[ SHCXX] ARM/cxx_config/BasicIntLink.cc -> .os
[ SHCXX] ARM/cxx_config/CoherentXBar.cc -> .os
[ SHCXX] src/dev/arm/css/mhu.cc -> ARM/dev/arm/css/mhu.os
[ SHCXX] ARM/python/_m5/param_ArmPMU.cc -> .os
[ SHCXX] src/cpu/o3/decode.cc -> ARM/cpu/o3/decode.os
[ SHCXX] src/dev/pixelpump.cc -> ARM/dev/pixelpump.os
[ SHCXX] src/dev/arm/timer_sp804.cc -> ARM/dev/arm/timer_sp804.os
[ SHCXX] ARM/cxx_config/DerivedClockDomain.cc -> .os
[ SHCXX] ARM/cxx_config/QoSMemCtrl.cc -> .os
[ SHCXX] ARM/python/_m5/param_BaseGic.cc -> .os
[ SHCXX] ARM/python/_m5/param_BasicIntLink.cc -> .os
[ SHCXX] ARM/python/_m5/param_CoherentXBar.cc -> .os
[ SHCXX] src/dev/serial/uart8250.cc -> ARM/dev/serial/uart8250.os
[ SHCXX] ARM/cxx_config/Scp.cc -> .os
[ SHCXX] ARM/cxx_config/NoncoherentCache.cc -> .os
[ SHCXX] src/mem/token_port.cc -> ARM/mem/token_port.os
[ SHCXX] src/cpu/o3/cpu.cc -> ARM/cpu/o3/cpu.os
[ SHCXX] src/cpu/testers/directedtest/InvalidateGenerator.cc ->
ARM/cpu/testers/directedtest/InvalidateGenerator.os
[ SHCXX] src/dev/arm/ssc.cc -> ARM/dev/arm/ssc.os
[ SHCXX] ARM/python/_m5/param_DerivedClockDomain.cc -> .os
[ SHCXX] ARM/cxx_config/GenericTimerMem.cc -> .os
[ SHCXX] ARM/python/_m5/param_QoSMemCtrl.cc -> .os
[ SHCXX] ARM/cxx_config/BasicExtLink.cc -> .os
[ SHCXX] ARM/cxx_config/NoncoherentXBar.cc -> .os
[ SHCXX] src/dev/serial/uart.cc -> ARM/dev/serial/uart.os
[ SHCXX] src/arch/arm/mmu.cc -> ARM/arch/arm/mmu.os
[CXXCPRCC] m5.objects.Uart, SimpleUart -> ARM/cxx_config/SimpleUart.cc
[SO Param] m5.objects.ThermalModel, ThermalReference ->
ARM/python/_m5/param_ThermalReference.cc
[SO Param] m5.objects.PciHost, PciHost -> ARM/params/PciHost.hh
[CXXCPRHH] m5.objects.Uart, SimpleUart -> ARM/cxx_config/SimpleUart.hh
[SO Param] m5.objects.Prefetcher, TaggedPrefetcher ->
ARM/params/TaggedPrefetcher.hh
[ SHCXX] ARM/python/_m5/param_Sinic.cc -> .os
[ SHCXX] ARM/cxx_config/SimpleUart.cc -> .os
[ SHCXX] src/mem/cache/prefetch/tagged.cc -> ARM/mem/cache/prefetch/tagged.os
[ SHCXX] ARM/cxx_config/TaggedPrefetcher.cc -> .os
[ SHCXX] ARM/python/_m5/param_TaggedPrefetcher.cc -> .os
[ SHCXX] ARM/cxx_config/EtherDevice.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciMemUpperBar.cc -> .os
[ SHCXX] src/dev/pci/host.cc -> ARM/dev/pci/host.os
[ SHCXX] ARM/python/_m5/param_IdeController.cc -> .os
[ SHCXX] ARM/cxx_config/PciBarNone.cc -> .os
[ SHCXX] ARM/cxx_config/PciDevice.cc -> .os
[ SHCXX] ARM/cxx_config/GenericArmPciHost.cc -> .os
[ SHCXX] ARM/cxx_config/CopyEngine.cc -> .os
[ SHCXX] ARM/python/_m5/param_EtherDevBase.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciLegacyIoBar.cc -> .os
[ SHCXX] src/dev/net/etherdevice.cc -> ARM/dev/net/etherdevice.os
[ SHCXX] src/dev/storage/ide_ctrl.cc -> ARM/dev/storage/ide_ctrl.os
[ SHCXX] ARM/python/_m5/param_PciHost.cc -> .os
[ SHCXX] ARM/cxx_config/NSGigE.cc -> .os
[ SHCXX] ARM/python/_m5/param_EtherDevice.cc -> .os
[ SHCXX] ARM/cxx_config/PciMemBar.cc -> .os
[ SHCXX] ARM/cxx_config/GenericPciHost.cc -> .os
[ SHCXX] src/dev/virtio/pci.cc -> ARM/dev/virtio/pci.os
[ SHCXX] src/dev/net/sinic.cc -> ARM/dev/net/sinic.os
[ SHCXX] ARM/cxx_config/IdeDisk.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciBarNone.cc -> .os
[ SHCXX] src/dev/arm/pci_host.cc -> ARM/dev/arm/pci_host.os
[ SHCXX] ARM/cxx_config/PciVirtIO.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciDevice.cc -> .os
[ SHCXX] ARM/python/_m5/param_GenericArmPciHost.cc -> .os
[ SHCXX] ARM/python/_m5/param_CopyEngine.cc -> .os
[ SHCXX] ARM/cxx_config/IGbE.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciBar.cc -> .os
[ SHCXX] ARM/cxx_config/PciIoBar.cc -> .os
[ SHCXX] ARM/python/_m5/param_NSGigE.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciMemBar.cc -> .os
[ SHCXX] ARM/python/_m5/param_GenericPciHost.cc -> .os
[ SHCXX] src/dev/net/ns_gige.cc -> ARM/dev/net/ns_gige.os
[ SHCXX] ARM/python/_m5/param_IdeDisk.cc -> .os
[ SHCXX] ARM/cxx_config/PciBar.cc -> .os
[ SHCXX] ARM/cxx_config/Sinic.cc -> .os
[ SHCXX] ARM/python/_m5/param_IGbE.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciVirtIO.cc -> .os
[ SHCXX] ARM/cxx_config/PciMemUpperBar.cc -> .os
[ SHCXX] ARM/cxx_config/IdeController.cc -> .os
[ SHCXX] ARM/python/_m5/param_PciIoBar.cc -> .os
[ SHCXX] src/dev/pci/device.cc -> ARM/dev/pci/device.os
[ SHCXX] src/dev/pci/copy_engine.cc -> ARM/dev/pci/copy_engine.os
[ SHCXX] ARM/cxx_config/EtherDevBase.cc -> .os
[ SHCXX] ARM/cxx_config/PciLegacyIoBar.cc -> .os
[ SHCXX] src/dev/storage/ide_disk.cc -> ARM/dev/storage/ide_disk.os
[ SHCXX] ARM/cxx_config/PciHost.cc -> .os
[ SHCXX] src/dev/net/i8254xGBe.cc -> ARM/dev/net/i8254xGBe.os
[SO Param] m5.objects.Ethernet, EtherTapBase ->
ARM/python/_m5/param_EtherTapBase.cc
[SO Param] m5.objects.ReplacementPolicies, MRURP ->
ARM/python/_m5/param_MRURP.cc
[CXXCPRCC] m5.objects.RubyDirectedTester, SeriesRequestGenerator ->
ARM/cxx_config/SeriesRequestGenerator.cc
[SO Param] m5.objects.ThermalModel, ThermalReference ->
ARM/params/ThermalReference.hh
[SO Param] m5.objects.Network, RubyNetwork ->
ARM/python/_m5/param_RubyNetwork.cc
[CXXCPRHH] m5.objects.RubyDirectedTester, SeriesRequestGenerator ->
ARM/cxx_config/SeriesRequestGenerator.hh
[SO Param] m5.objects.Ethernet, EtherTapBase -> ARM/params/EtherTapBase.hh
[ SHCXX] src/sim/power/thermal_model.cc -> ARM/sim/power/thermal_model.os
[ SHCXX] ARM/python/_m5/param_RubyNetwork.cc -> .os
[ SHCXX] ARM/cxx_config/SeriesRequestGenerator.cc -> .os
[ SHCXX] ARM/python/_m5/param_ThermalReference.cc -> .os
[ SHCXX] ARM/python/_m5/param_EtherTapStub.cc -> .os
[ SHCXX] ARM/cxx_config/EtherTapBase.cc -> .os
[ SHCXX] ARM/python/_m5/param_EtherTapBase.cc -> .os
[ SHCXX] ARM/cxx_config/EtherTap.cc -> .os
[ SHCXX] ARM/python/_m5/param_EtherTap.cc -> .os
[ SHCXX] ARM/cxx_config/EtherTapStub.cc -> .os
[ SHCXX] src/dev/net/ethertap.cc -> ARM/dev/net/ethertap.os
[ SHCXX] ARM/cxx_config/ThermalReference.cc -> .os
[SO Param] m5.objects.ArmMMU, ArmTableWalker ->
ARM/python/_m5/param_ArmTableWalker.cc
[SO Param] m5.objects.Controller, RubyController ->
ARM/python/_m5/param_RubyController.cc
[ SHCXX] ARM/python/_m5/param_ArmTableWalker.cc -> .os
[SO Param] m5.objects.ReplacementPolicies, MRURP -> ARM/params/MRURP.hh
[ SHCXX] ARM/python/_m5/param_RubyController.cc -> .os
[ SHCXX] src/mem/cache/replacement_policies/mru_rp.cc ->
ARM/mem/cache/replacement_policies/mru_rp.os
[ SHCXX] ARM/python/_m5/param_MRURP.cc -> .os
[ SHCXX] ARM/cxx_config/MRURP.cc -> .os
[ SHCXX] src/base/date.cc -> ARM/base/date.os
[ SHLINK] -> ARM/libgem5_opt.so
scons: done building targets.
*** Summary of Warnings ***
Warning: Header file <png.h> not found.
This host has no libpng library.
Disabling support for PNG framebuffers.
Warning: Couldn't find HDF5 C++ libraries. Disabling HDF5 support.
Warning: While checking protoc version: [Errno 2] No such file or directory:
'protoc'
Warning: Protocol buffer compiler (protoc) not found.
Please install protobuf-compiler for tracing support.
+ docker run -u 118: --volume
/nobackup/jenkins/workspace/nightly/tests/..:/nobackup/jenkins/workspace/nightly/tests/..
-w /nobackup/jenkins/workspace/nightly/tests/.. --memory=18g --rm
gcr.io/gem5-test/systemc-env:latest bash -c 'cd
util/systemc/gem5_within_systemc && make -j24 && ../../../build/ARM/gem5.opt
../../../configs/deprecated/example/se.py -c
../../../tests/test-progs/hello/bin/arm/linux/hello &&
LD_LIBRARY_PATH=../../../build/ARM/:/opt/systemc/lib-linux64/ ./gem5.opt.sc
m5out/config.ini && cd -; '
Unable to find image 'gcr.io/gem5-test/systemc-env:latest' locally
latest: Pulling from gem5-test/systemc-env
2ab09b027e7f: Pulling fs layer
f438dcd32ad7: Pulling fs layer
ef7783eb7444: Pulling fs layer
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bdb74477465f: Pulling fs layer
b0dbdb201993: Waiting
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e625e43617cb: Waiting
eb91ea97e7af: Waiting
e317c39080c7: Waiting
ef7783eb7444: Verifying Checksum
ef7783eb7444: Download complete
2ab09b027e7f: Verifying Checksum
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e625e43617cb: Download complete
bdb74477465f: Download complete
2ab09b027e7f: Pull complete
f438dcd32ad7: Verifying Checksum
f438dcd32ad7: Download complete
f438dcd32ad7: Pull complete
ef7783eb7444: Pull complete
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Digest: sha256:53ba4fc28d67336826f67d17e2cd5c32b4f585d55addf9edb1040c265c76f6ac
Status: Downloaded newer image for gcr.io/gem5-test/systemc-env:latest
g++ -I../../../build/ARM -L../../../build/ARM -I../../../ext/
-I/opt/systemc/include -L/opt/systemc/lib-linux64 -std=c++17 -g -DTRACING_ON -c
-o main.o main.cc
g++ -I../../../build/ARM -L../../../build/ARM -I../../../ext/
-I/opt/systemc/include -L/opt/systemc/lib-linux64 -std=c++17 -g -DTRACING_ON -c
-o stats.o stats.cc
g++ -I../../../build/ARM -L../../../build/ARM -I../../../ext/
-I/opt/systemc/include -L/opt/systemc/lib-linux64 -std=c++17 -g -DTRACING_ON -c
-o sc_gem5_control.o sc_gem5_control.cc
g++ -I../../../build/ARM -L../../../build/ARM -I../../../ext/
-I/opt/systemc/include -L/opt/systemc/lib-linux64 -std=c++17 -g -DTRACING_ON -c
-o sc_logger.o sc_logger.cc
g++ -I../../../build/ARM -L../../../build/ARM -I../../../ext/
-I/opt/systemc/include -L/opt/systemc/lib-linux64 -std=c++17 -g -DTRACING_ON -c
-o sc_module.o sc_module.cc
sc_module.cc:56:10: fatal error: base/compiler.hh: No such file or directory
56 | #include "base/compiler.hh"
| ^~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [Makefile:53: sc_module.o] Error 1
make: *** Waiting for unfinished jobs....
stats.cc:49:10: fatal error: base/logging.hh: No such file or directory
49 | #include "base/logging.hh"
| ^~~~~~~~~~~~~~~~~
compilation terminated.
sc_gem5_control.cc:42:10: fatal error: base/statistics.hh: No such file or
directory
42 | #include "base/statistics.hh"
| ^~~~~~~~~~~~~~~~~~~~
compilation terminated.
make: *** [Makefile:53: stats.o] Error 1
make: *** [Makefile:53: sc_gem5_control.o] Error 1
main.cc:59:10: fatal error: base/statistics.hh: No such file or directory
59 | #include "base/statistics.hh"
| ^~~~~~~~~~~~~~~~~~~~
compilation terminated.
In file included from sc_logger.cc:49:
sc_logger.hh:50:10: fatal error: base/trace.hh: No such file or directory
50 | #include "base/trace.hh"
| ^~~~~~~~~~~~~~~
compilation terminated.
make: *** [Makefile:53: main.o] Error 1
make: *** [Makefile:53: sc_logger.o] Error 1
Build step 'Execute shell' marked build as failure
Archiving artifacts
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