Matthew Poremba has uploaded this change for review. (
https://gem5-review.googlesource.com/c/public/gem5/+/71899?usp=email )
Change subject: arch-vega: Add Vega D16 decodings and fix V_SWAP_B32
......................................................................
arch-vega: Add Vega D16 decodings and fix V_SWAP_B32
Vega adds multiple new D16 instructions which load a byte or short into
the lower or upper 16 bits of a register for packed math. The decoder
table has subDecode tables for FLAT instructions which represents 32
opcodes in each subDecode table. The subDecode table for opcodes 32-63
is missing so it is added here.
The opcode for V_SWAP_B32 is also off by one- In the ISA manual this
instruction is opcode 81, the instruction before is 79, and there is no
opcode 80, so the decoder entry is swapped with the invalid decoding
below it.
Change-Id: I278fea574ea684ccc6302d5b4d0f5dd8813a88ad
---
M src/arch/amdgpu/vega/decoder.cc
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/arch/amdgpu/vega/decoder.cc
b/src/arch/amdgpu/vega/decoder.cc
index fd3a803..a86dd66 100644
--- a/src/arch/amdgpu/vega/decoder.cc
+++ b/src/arch/amdgpu/vega/decoder.cc
@@ -495,7 +495,7 @@
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::subDecode_OP_FLAT,
- &Decoder::decode_invalid,
+ &Decoder::subDecode_OP_FLAT,
&Decoder::subDecode_OP_FLAT,
&Decoder::subDecode_OP_FLAT,
&Decoder::decode_invalid,
@@ -3140,8 +3140,8 @@
&Decoder::decode_OP_VOP1__V_CVT_NORM_I16_F16,
&Decoder::decode_OP_VOP1__V_CVT_NORM_U16_F16,
&Decoder::decode_OP_VOP1__V_SAT_PK_U8_I16,
- &Decoder::decode_OP_VOP1__V_SWAP_B32,
&Decoder::decode_invalid,
+ &Decoder::decode_OP_VOP1__V_SWAP_B32,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
&Decoder::decode_invalid,
--
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Gerrit-MessageType: newchange
Gerrit-Project: public/gem5
Gerrit-Branch: develop
Gerrit-Change-Id: I278fea574ea684ccc6302d5b4d0f5dd8813a88ad
Gerrit-Change-Number: 71899
Gerrit-PatchSet: 1
Gerrit-Owner: Matthew Poremba <matthew.pore...@amd.com>
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