I have split reads working (I think), and now I'm starting in on writes. The write function is a little more convoluted than the read function, partly because it tries to always have a dcache_pkt around even when there hasn't been an access since that's passed to completeAcc. The only time completeAcc is called inline with initiateAcc, which is where read/write is called, is if the CPU is still running, aka not waiting for the dcache, and there was no fault. The only way this can happen is if either the instruction itself never did an access, which can be the case with ARM apparently, or if the instruction is a store conditional which tried to do an access but failed for some reason before the actual packet got sent. In both of these cases, rather than make sure that some nonsense dcache_pkt is around so completeAcc doesn't get a NULL pointer, would it make sense to just not call it at all? The Alpha memory instructions are a little too tangled for me to be confident whether that would be ok. It looks like they're actually made up of a few instructions?
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