changeset 76abee886def in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=76abee886def
description:
Add in Context IDs to the simulator. From now on, cpuId is almost
never used,
the primary identifier for a hardware context should be contextId().
The
concept of threads within a CPU remains, in the form of threadId()
because
sometimes you need to know which context within a cpu to manipulate.
diffstat:
23 files changed, 29 insertions(+), 24 deletions(-)
src/arch/alpha/locked_mem.hh | 2 +-
src/arch/mips/locked_mem.hh | 2 +-
src/arch/sparc/ua2005.cc | 2 +-
src/cpu/base.cc | 2 +-
src/cpu/base_dyn_inst.hh | 1 +
src/cpu/checker/cpu_impl.hh | 1 -
src/cpu/o3/cpu.cc | 1 -
src/cpu/o3/thread_context.hh | 2 ++
src/cpu/simple_thread.cc | 1 +
src/cpu/thread_context.cc | 2 ++
src/cpu/thread_context.hh | 3 +++
src/cpu/thread_state.hh | 2 ++
src/dev/alpha/tsunami_cchip.cc | 4 +++-
src/mem/cache/blk.hh | 3 +--
src/mem/cache/prefetch/base.cc | 1 -
src/mem/cache/prefetch/ghb.cc | 4 ++--
src/mem/cache/prefetch/ghb.hh | 2 +-
src/mem/cache/prefetch/stride.cc | 4 ++--
src/mem/cache/prefetch/stride.hh | 2 +-
src/mem/physical.cc | 4 ++--
src/mem/physical.hh | 3 +--
src/mem/request.hh | 3 ---
src/sim/system.hh | 2 +-
diffs (truncated from 848 to 300 lines):
diff -r 993c7952b930 -r 76abee886def src/arch/alpha/locked_mem.hh
--- a/src/arch/alpha/locked_mem.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/arch/alpha/locked_mem.hh Sun Nov 02 21:57:07 2008 -0500
@@ -85,9 +85,9 @@
stCondFailures++;
xc->setStCondFailures(stCondFailures);
if (stCondFailures % 100000 == 0) {
- warn("cpu %d: %d consecutive "
+ warn("context %d: %d consecutive "
"store conditional failures\n",
- xc->cpuId(), stCondFailures);
+ xc->contextId(), stCondFailures);
}
// store conditional failed already, so don't issue it to mem
diff -r 993c7952b930 -r 76abee886def src/arch/mips/locked_mem.hh
--- a/src/arch/mips/locked_mem.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/arch/mips/locked_mem.hh Sun Nov 02 21:57:07 2008 -0500
@@ -83,9 +83,9 @@
stCondFailures++;
xc->setStCondFailures(stCondFailures);
if (stCondFailures % 10 == 0) {
- warn("%i: cpu %d: %d consecutive "
+ warn("%i: context %d: %d consecutive "
"store conditional failures\n",
- curTick, xc->cpuId(), stCondFailures);
+ curTick, xc->contextId(), stCondFailures);
}
if (stCondFailures == 5000) {
diff -r 993c7952b930 -r 76abee886def src/arch/sparc/ua2005.cc
--- a/src/arch/sparc/ua2005.cc Sun Nov 02 21:57:06 2008 -0500
+++ b/src/arch/sparc/ua2005.cc Sun Nov 02 21:57:07 2008 -0500
@@ -257,11 +257,11 @@
temp = readRegNoEffect(miscReg) & (STS::active | STS::speculative);
// Check that the CPU array is fully populated
// (by calling getNumCPus())
- assert(sys->getNumCPUs() > tc->cpuId());
+ assert(sys->getNumContexts() > tc->contextId());
- temp |= tc->cpuId() << STS::shft_id;
+ temp |= tc->contextId() << STS::shft_id;
- for (x = tc->cpuId() & ~3; x < sys->threadContexts.size(); x++) {
+ for (x = tc->contextId() & ~3; x < sys->threadContexts.size(); x++) {
switch (sys->threadContexts[x]->status()) {
case ThreadContext::Active:
temp |= STS::st_run << (STS::shft_fsm0 -
diff -r 993c7952b930 -r 76abee886def src/arch/x86/tlb.cc
--- a/src/arch/x86/tlb.cc Sun Nov 02 21:57:06 2008 -0500
+++ b/src/arch/x86/tlb.cc Sun Nov 02 21:57:07 2008 -0500
@@ -654,7 +654,7 @@
*/
// Force the access to be uncacheable.
req->setFlags(req->getFlags() | UNCACHEABLE);
- req->setPaddr(x86LocalAPICAddress(tc->cpuId(), paddr - baseAddr));
+ req->setPaddr(x86LocalAPICAddress(tc->contextId(), paddr - baseAddr));
}
#endif
return NoFault;
diff -r 993c7952b930 -r 76abee886def src/cpu/base.cc
--- a/src/cpu/base.cc Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/base.cc Sun Nov 02 21:57:07 2008 -0500
@@ -285,9 +285,9 @@
for (int i = 0; i < threadContexts.size(); ++i) {
ThreadContext *tc = threadContexts[i];
- system->registerThreadContext(tc);
+ tc->setContextId(system->registerThreadContext(tc));
#if !FULL_SYSTEM
- tc->getProcessPtr()->assignThreadContext(tc->cpuId());
+ tc->getProcessPtr()->assignThreadContext(tc->contextId());
#endif
}
}
@@ -328,8 +328,8 @@
CpuEvent::replaceThreadContext(oldTC, newTC);
- assert(newTC->cpuId() == oldTC->cpuId());
- system->replaceThreadContext(newTC, newTC->cpuId());
+ assert(newTC->contextId() == oldTC->contextId());
+ system->replaceThreadContext(newTC, newTC->contextId());
if (DTRACE(Context))
ThreadContext::compare(oldTC, newTC);
diff -r 993c7952b930 -r 76abee886def src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/base_dyn_inst.hh Sun Nov 02 21:57:07 2008 -0500
@@ -414,6 +414,9 @@
/** Read this CPU's ID. */
int cpuId() { return cpu->cpuId(); }
+ /** Read this context's system-wide ID **/
+ int contextId() { return thread->contextId(); }
+
/** Returns the fault type. */
Fault getFault() { return fault; }
@@ -868,7 +871,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->cpuId(), threadNumber);
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataReadReq(req, thread);
@@ -887,7 +890,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->cpuId(), threadNumber);
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataReadReq(req, thread);
@@ -942,7 +945,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, vaddr, size, flags, PC);
- req->setThreadContext(thread->cpuId(), threadNumber);
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataWriteReq(req, thread);
@@ -966,7 +969,7 @@
reqMade = true;
Request *req = new Request();
req->setVirt(asid, addr, sizeof(T), flags, this->PC);
- req->setThreadContext(thread->cpuId(), threadNumber);
+ req->setThreadContext(thread->contextId(), threadNumber);
fault = cpu->translateDataWriteReq(req, thread);
diff -r 993c7952b930 -r 76abee886def src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/checker/cpu_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -152,7 +152,8 @@
memReq = new Request(inst->threadNumber, fetch_PC,
sizeof(uint32_t),
IFETCH_FLAGS(thread->readPC()),
- fetch_PC, thread->cpuId(), inst->threadNumber);
+ fetch_PC, thread->contextId(),
+ inst->threadNumber);
bool succeeded = translateInstReq(memReq);
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/cpu.cc Sun Nov 02 21:57:07 2008 -0500
@@ -589,9 +589,7 @@
void
FullO3CPU<Impl>::init()
{
- if (!deferRegistration) {
- registerThreadContexts();
- }
+ BaseCPU::init();
// Set inSyscall so that the CPU doesn't squash when initially
// setting up registers.
@@ -610,7 +608,7 @@
}
#if FULL_SYSTEM
- TheISA::initCPU(src_tc, src_tc->cpuId());
+ TheISA::initCPU(src_tc, src_tc->contextId());
#endif
}
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/fetch_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -362,7 +362,7 @@
void
DefaultFetch<Impl>::processCacheCompletion(PacketPtr pkt)
{
- unsigned tid = pkt->req->getThreadNum();
+ unsigned tid = pkt->req->threadId();
DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n",tid);
@@ -593,7 +593,8 @@
// Set the appropriate read size and flags as well.
// Build request here.
RequestPtr mem_req = new Request(tid, block_PC, cacheBlkSize, 0,
- fetch_PC, cpu->cpuId(), tid);
+ fetch_PC, cpu->thread[tid]->contextId(),
+ tid);
memReq[tid] = mem_req;
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/lsq.hh
--- a/src/cpu/o3/lsq.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/lsq.hh Sun Nov 02 21:57:07 2008 -0500
@@ -371,7 +371,7 @@
Fault
LSQ<Impl>::read(RequestPtr req, T &data, int load_idx)
{
- unsigned tid = req->getThreadNum();
+ unsigned tid = req->threadId();
return thread[tid].read(req, data, load_idx);
}
@@ -381,7 +381,7 @@
Fault
LSQ<Impl>::write(RequestPtr req, T &data, int store_idx)
{
- unsigned tid = req->getThreadNum();
+ unsigned tid = req->threadId();
return thread[tid].write(req, data, store_idx);
}
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/lsq_impl.hh
--- a/src/cpu/o3/lsq_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/lsq_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -85,7 +85,7 @@
if (pkt->isError())
DPRINTF(LSQ, "Got error packet back for address: %#X\n",
pkt->getAddr());
if (pkt->isResponse()) {
- lsq->thread[pkt->req->getThreadNum()].completeDataAccess(pkt);
+ lsq->thread[pkt->req->threadId()].completeDataAccess(pkt);
}
else {
// must be a snoop
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/thread_context.hh
--- a/src/cpu/o3/thread_context.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/thread_context.hh Sun Nov 02 21:57:07 2008 -0500
@@ -77,6 +77,10 @@
/** Reads this CPU's ID. */
virtual int cpuId() { return cpu->cpuId(); }
+
+ virtual int contextId() { return thread->contextId(); }
+
+ virtual void setContextId(int id) { thread->setContextId(id); }
#if FULL_SYSTEM
/** Returns a pointer to the system. */
diff -r 993c7952b930 -r 76abee886def src/cpu/o3/thread_context_impl.hh
--- a/src/cpu/o3/thread_context_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/o3/thread_context_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -63,6 +63,7 @@
// copy over functional state
setStatus(old_context->status());
copyArchRegs(old_context);
+ setContextId(old_context->contextId());
#if !FULL_SYSTEM
thread->funcExeInst = old_context->readFuncExeInst();
diff -r 993c7952b930 -r 76abee886def src/cpu/ozone/cpu_impl.hh
--- a/src/cpu/ozone/cpu_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/ozone/cpu_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -417,7 +417,7 @@
ThreadContext *tc = threadContexts[i];
// initialize CPU, including PC
- TheISA::initCPU(tc, tc->cpuId());
+ TheISA::initCPU(tc, tc->contextId());
}
#endif
frontEnd->renameTable.copyFrom(thread.renameTable);
@@ -736,14 +736,6 @@
template <class Impl>
void
-OzoneCPU<Impl>::OzoneTC::setCpuId(int id)
-{
- cpu->cpuId = id;
- thread->setCpuId(id);
-}
-
-template <class Impl>
-void
OzoneCPU<Impl>::OzoneTC::setStatus(Status new_status)
{
thread->setStatus(new_status);
@@ -804,6 +796,7 @@
setStatus(old_context->status());
copyArchRegs(old_context);
setCpuId(old_context->cpuId());
+ setContextId(old_context->contextId());
thread->setInst(old_context->getInst());
#if !FULL_SYSTEM
diff -r 993c7952b930 -r 76abee886def src/cpu/ozone/front_end_impl.hh
--- a/src/cpu/ozone/front_end_impl.hh Sun Nov 02 21:57:06 2008 -0500
+++ b/src/cpu/ozone/front_end_impl.hh Sun Nov 02 21:57:07 2008 -0500
@@ -477,7 +477,7 @@
// Setup the memReq to do a read of the first isntruction's address.
// Set the appropriate read size and flags as well.
memReq = new Request(0, fetch_PC, cacheBlkSize, 0,
- PC, cpu->cpuId(), 0);
+ PC, cpu->thread->contextId());
// Translate the instruction request.
fault = cpu->translateInstReq(memReq, thread);
diff -r 993c7952b930 -r 76abee886def src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc Sun Nov 02 21:57:06 2008 -0500
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