I sort of doubt it... parser has always been a bit nondeterministic, where this is just a subtle and unforeseen but deterministic side effect of a bug fix.
Steve On Mon, Nov 17, 2008 at 11:57 AM, nathan binkert <[EMAIL PROTECTED]> wrote: > Ah, so that was you. That makes sense. I seriously wonder if this or > something like it is the problem with 20.parser. > > Nate > > On Mon, Nov 17, 2008 at 11:11 AM, Steve Reinhardt <[EMAIL PROTECTED]> wrote: >> changeset c5447915af50 in /z/repo/m5 >> details: http://repo.m5sim.org/m5?cmd=changeset;node=c5447915af50 >> description: >> Update stats for brk fix (cset f28f020f3006). >> >> diffstat: >> >> 2 files changed, 3 insertions(+), 8 deletions(-) >> tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt | 6 ++---- >> tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout | 5 +---- >> >> diffs (237 lines): >> >> diff -r 7015e400bd1d -r c5447915af50 >> tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt >> --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Sat >> Nov 15 23:42:11 2008 -0500 >> +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/m5stats.txt Mon >> Nov 17 14:11:09 2008 -0500 >> @@ -1,13 +1,13 @@ >> >> ---------- Begin Simulation Statistics ---------- >> -host_inst_rate 1243989 >> # Simulator instruction rate (inst/s) >> -host_mem_usage 207864 >> # Number of bytes of host memory used >> -host_seconds 155.50 >> # Real time elapsed on the host >> -host_tick_rate 1740014863 >> # Simulator tick rate (ticks/s) >> +host_inst_rate 1229412 >> # Simulator instruction rate (inst/s) >> +host_mem_usage 207888 >> # Number of bytes of host memory used >> +host_seconds 157.35 >> # Real time elapsed on the host >> +host_tick_rate 1719613407 >> # Simulator tick rate (ticks/s) >> sim_freq 1000000000000 >> # Frequency of simulated ticks >> sim_insts 193444769 >> # Number of instructions simulated >> sim_seconds 0.270579 >> # Number of seconds simulated >> -sim_ticks 270578958000 >> # Number of ticks simulated >> +sim_ticks 270578573000 >> # Number of ticks simulated >> system.cpu.dcache.ReadReq_accesses 57735069 >> # number of ReadReq accesses(hits+misses) >> system.cpu.dcache.ReadReq_avg_miss_latency 56000 >> # average ReadReq miss latency >> system.cpu.dcache.ReadReq_avg_mshr_miss_latency 53000 >> # average ReadReq mshr miss latency >> @@ -31,16 +31,16 @@ >> system.cpu.dcache.WriteReq_accesses 18976439 >> # number of WriteReq accesses(hits+misses) >> system.cpu.dcache.WriteReq_avg_miss_latency 56000 >> # average WriteReq miss latency >> system.cpu.dcache.WriteReq_avg_mshr_miss_latency 53000 >> # average WriteReq mshr miss latency >> -system.cpu.dcache.WriteReq_hits 18975331 >> # number of WriteReq hits >> -system.cpu.dcache.WriteReq_miss_latency 62048000 >> # number of WriteReq miss cycles >> +system.cpu.dcache.WriteReq_hits 18975338 >> # number of WriteReq hits >> +system.cpu.dcache.WriteReq_miss_latency 61656000 >> # number of WriteReq miss cycles >> system.cpu.dcache.WriteReq_miss_rate 0.000058 >> # miss rate for WriteReq accesses >> -system.cpu.dcache.WriteReq_misses 1108 >> # number of WriteReq misses >> -system.cpu.dcache.WriteReq_mshr_miss_latency 58724000 >> # number of WriteReq MSHR miss cycles >> +system.cpu.dcache.WriteReq_misses 1101 >> # number of WriteReq misses >> +system.cpu.dcache.WriteReq_mshr_miss_latency 58353000 >> # number of WriteReq MSHR miss cycles >> system.cpu.dcache.WriteReq_mshr_miss_rate 0.000058 >> # mshr miss rate for WriteReq accesses >> -system.cpu.dcache.WriteReq_mshr_misses 1108 >> # number of WriteReq MSHR misses >> +system.cpu.dcache.WriteReq_mshr_misses 1101 >> # number of WriteReq MSHR misses >> system.cpu.dcache.avg_blocked_cycles_no_mshrs <err: div-0> >> # average number of cycles each access was blocked >> system.cpu.dcache.avg_blocked_cycles_no_targets <err: div-0> >> # average number of cycles each access was blocked >> -system.cpu.dcache.avg_refs 48472.729627 >> # Average number of references to valid blocks. >> +system.cpu.dcache.avg_refs 48688.031726 >> # Average number of references to valid blocks. >> system.cpu.dcache.blocked_no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.dcache.blocked_no_targets 0 >> # number of cycles access was blocked >> system.cpu.dcache.blocked_cycles_no_mshrs 0 >> # number of cycles access was blocked >> @@ -49,14 +49,14 @@ >> system.cpu.dcache.demand_accesses 76711508 >> # number of demand (read+write) accesses >> system.cpu.dcache.demand_avg_miss_latency 56000 >> # average overall miss latency >> system.cpu.dcache.demand_avg_mshr_miss_latency 53000 >> # average overall mshr miss latency >> -system.cpu.dcache.demand_hits 76709902 >> # number of demand (read+write) hits >> -system.cpu.dcache.demand_miss_latency 89936000 >> # number of demand (read+write) miss cycles >> +system.cpu.dcache.demand_hits 76709909 >> # number of demand (read+write) hits >> +system.cpu.dcache.demand_miss_latency 89544000 >> # number of demand (read+write) miss cycles >> system.cpu.dcache.demand_miss_rate 0.000021 >> # miss rate for demand accesses >> -system.cpu.dcache.demand_misses 1606 >> # number of demand (read+write) misses >> +system.cpu.dcache.demand_misses 1599 >> # number of demand (read+write) misses >> system.cpu.dcache.demand_mshr_hits 0 >> # number of demand (read+write) MSHR hits >> -system.cpu.dcache.demand_mshr_miss_latency 85118000 >> # number of demand (read+write) MSHR miss cycles >> +system.cpu.dcache.demand_mshr_miss_latency 84747000 >> # number of demand (read+write) MSHR miss cycles >> system.cpu.dcache.demand_mshr_miss_rate 0.000021 >> # mshr miss rate for demand accesses >> -system.cpu.dcache.demand_mshr_misses 1606 >> # number of demand (read+write) MSHR misses >> +system.cpu.dcache.demand_mshr_misses 1599 >> # number of demand (read+write) MSHR misses >> system.cpu.dcache.fast_writes 0 >> # number of fast writes performed >> system.cpu.dcache.mshr_cap_events 0 >> # number of times MSHR cap was activated >> system.cpu.dcache.no_allocate_misses 0 >> # Number of misses that were no-allocate >> @@ -64,14 +64,14 @@ >> system.cpu.dcache.overall_avg_miss_latency 56000 >> # average overall miss latency >> system.cpu.dcache.overall_avg_mshr_miss_latency 53000 >> # average overall mshr miss latency >> system.cpu.dcache.overall_avg_mshr_uncacheable_latency <err: div-0> >> # average overall mshr uncacheable latency >> -system.cpu.dcache.overall_hits 76709902 >> # number of overall hits >> -system.cpu.dcache.overall_miss_latency 89936000 >> # number of overall miss cycles >> +system.cpu.dcache.overall_hits 76709909 >> # number of overall hits >> +system.cpu.dcache.overall_miss_latency 89544000 >> # number of overall miss cycles >> system.cpu.dcache.overall_miss_rate 0.000021 >> # miss rate for overall accesses >> -system.cpu.dcache.overall_misses 1606 >> # number of overall misses >> +system.cpu.dcache.overall_misses 1599 >> # number of overall misses >> system.cpu.dcache.overall_mshr_hits 0 >> # number of overall MSHR hits >> -system.cpu.dcache.overall_mshr_miss_latency 85118000 >> # number of overall MSHR miss cycles >> +system.cpu.dcache.overall_mshr_miss_latency 84747000 >> # number of overall MSHR miss cycles >> system.cpu.dcache.overall_mshr_miss_rate 0.000021 >> # mshr miss rate for overall accesses >> -system.cpu.dcache.overall_mshr_misses 1606 >> # number of overall MSHR misses >> +system.cpu.dcache.overall_mshr_misses 1599 >> # number of overall MSHR misses >> system.cpu.dcache.overall_mshr_uncacheable_latency 0 >> # number of overall MSHR uncacheable cycles >> system.cpu.dcache.overall_mshr_uncacheable_misses 0 >> # number of overall MSHR uncacheable misses >> system.cpu.dcache.prefetcher.num_hwpf_already_in_cache 0 >> # number of hwpf that were already in the cache >> @@ -83,13 +83,13 @@ >> system.cpu.dcache.prefetcher.num_hwpf_removed_MSHR_hit 0 >> # number of hwpf removed because MSHR allocated >> system.cpu.dcache.prefetcher.num_hwpf_span_page 0 >> # number of hwpf spanning a virtual page >> system.cpu.dcache.prefetcher.num_hwpf_squashed_from_miss 0 >> # number of hwpf that got squashed due to a miss aborting >> calculation time >> -system.cpu.dcache.replacements 26 >> # number of replacements >> -system.cpu.dcache.sampled_refs 1583 >> # Sample count of references to valid blocks. >> +system.cpu.dcache.replacements 2 >> # number of replacements >> +system.cpu.dcache.sampled_refs 1576 >> # Sample count of references to valid blocks. >> system.cpu.dcache.soft_prefetch_mshr_full 0 >> # number of mshr full events for SW prefetching instrutions >> -system.cpu.dcache.tagsinuse 1235.200907 >> # Cycle average of tags in use >> -system.cpu.dcache.total_refs 76732331 >> # Total number of references to valid blocks. >> +system.cpu.dcache.tagsinuse 1237.193452 >> # Cycle average of tags in use >> +system.cpu.dcache.total_refs 76732338 >> # Total number of references to valid blocks. >> system.cpu.dcache.warmup_cycle 0 >> # Cycle when the warmup percentage was hit. >> -system.cpu.dcache.writebacks 23 >> # number of writebacks >> +system.cpu.dcache.writebacks 2 >> # number of writebacks >> system.cpu.icache.ReadReq_accesses 193445787 >> # number of ReadReq accesses(hits+misses) >> system.cpu.icache.ReadReq_avg_miss_latency 26294.433594 >> # average ReadReq miss latency >> system.cpu.icache.ReadReq_avg_mshr_miss_latency 23294.433594 >> # average ReadReq mshr miss latency >> @@ -148,20 +148,20 @@ >> system.cpu.icache.replacements 10362 >> # number of replacements >> system.cpu.icache.sampled_refs 12288 >> # Sample count of references to valid blocks. >> system.cpu.icache.soft_prefetch_mshr_full 0 >> # number of mshr full events for SW prefetching instrutions >> -system.cpu.icache.tagsinuse 1591.567399 >> # Cycle average of tags in use >> +system.cpu.icache.tagsinuse 1591.566927 >> # Cycle average of tags in use >> system.cpu.icache.total_refs 193433499 >> # Total number of references to valid blocks. >> system.cpu.icache.warmup_cycle 0 >> # Cycle when the warmup percentage was hit. >> system.cpu.icache.writebacks 0 >> # number of writebacks >> system.cpu.idle_fraction 0 >> # Percentage of idle cycles >> -system.cpu.l2cache.ReadExReq_accesses 1085 >> # number of ReadExReq accesses(hits+misses) >> +system.cpu.l2cache.ReadExReq_accesses 1078 >> # number of ReadExReq accesses(hits+misses) >> system.cpu.l2cache.ReadExReq_avg_miss_latency 52000 >> # average ReadExReq miss latency >> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency 40000 >> # average ReadExReq mshr miss latency >> -system.cpu.l2cache.ReadExReq_miss_latency 56420000 >> # number of ReadExReq miss cycles >> +system.cpu.l2cache.ReadExReq_miss_latency 56056000 >> # number of ReadExReq miss cycles >> system.cpu.l2cache.ReadExReq_miss_rate 1 >> # miss rate for ReadExReq accesses >> -system.cpu.l2cache.ReadExReq_misses 1085 >> # number of ReadExReq misses >> -system.cpu.l2cache.ReadExReq_mshr_miss_latency 43400000 >> # number of ReadExReq MSHR miss cycles >> +system.cpu.l2cache.ReadExReq_misses 1078 >> # number of ReadExReq misses >> +system.cpu.l2cache.ReadExReq_mshr_miss_latency 43120000 >> # number of ReadExReq MSHR miss cycles >> system.cpu.l2cache.ReadExReq_mshr_miss_rate 1 >> # mshr miss rate for ReadExReq accesses >> -system.cpu.l2cache.ReadExReq_mshr_misses 1085 >> # number of ReadExReq MSHR misses >> +system.cpu.l2cache.ReadExReq_mshr_misses 1078 >> # number of ReadExReq MSHR misses >> system.cpu.l2cache.ReadReq_accesses 12786 >> # number of ReadReq accesses(hits+misses) >> system.cpu.l2cache.ReadReq_avg_miss_latency 52000 >> # average ReadReq miss latency >> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency 40000 >> # average ReadReq mshr miss latency >> @@ -181,42 +181,42 @@ >> system.cpu.l2cache.UpgradeReq_mshr_miss_latency 1000000 >> # number of UpgradeReq MSHR miss cycles >> system.cpu.l2cache.UpgradeReq_mshr_miss_rate 1 >> # mshr miss rate for UpgradeReq accesses >> system.cpu.l2cache.UpgradeReq_mshr_misses 25 >> # number of UpgradeReq MSHR misses >> -system.cpu.l2cache.Writeback_accesses 23 >> # number of Writeback accesses(hits+misses) >> -system.cpu.l2cache.Writeback_hits 23 >> # number of Writeback hits >> +system.cpu.l2cache.Writeback_accesses 2 >> # number of Writeback accesses(hits+misses) >> +system.cpu.l2cache.Writeback_hits 2 >> # number of Writeback hits >> system.cpu.l2cache.avg_blocked_cycles_no_mshrs <err: div-0> >> # average number of cycles each access was blocked >> system.cpu.l2cache.avg_blocked_cycles_no_targets <err: div-0> >> # average number of cycles each access was blocked >> -system.cpu.l2cache.avg_refs 2.127019 >> # Average number of references to valid blocks. >> +system.cpu.l2cache.avg_refs 2.134332 >> # Average number of references to valid blocks. >> system.cpu.l2cache.blocked_no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked_no_targets 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked_cycles_no_mshrs 0 >> # number of cycles access was blocked >> system.cpu.l2cache.blocked_cycles_no_targets 0 >> # number of cycles access was blocked >> system.cpu.l2cache.cache_copies 0 >> # number of cache copies performed >> -system.cpu.l2cache.demand_accesses 13871 >> # number of demand (read+write) accesses >> +system.cpu.l2cache.demand_accesses 13864 >> # number of demand (read+write) accesses >> system.cpu.l2cache.demand_avg_miss_latency 52000 >> # average overall miss latency >> system.cpu.l2cache.demand_avg_mshr_miss_latency 40000 >> # average overall mshr miss latency >> system.cpu.l2cache.demand_hits 8691 >> # number of demand (read+write) hits >> -system.cpu.l2cache.demand_miss_latency 269360000 >> # number of demand (read+write) miss cycles >> -system.cpu.l2cache.demand_miss_rate 0.373441 >> # miss rate for demand accesses >> -system.cpu.l2cache.demand_misses 5180 >> # number of demand (read+write) misses >> +system.cpu.l2cache.demand_miss_latency 268996000 >> # number of demand (read+write) miss cycles >> +system.cpu.l2cache.demand_miss_rate 0.373125 >> # miss rate for demand accesses >> +system.cpu.l2cache.demand_misses 5173 >> # number of demand (read+write) misses >> system.cpu.l2cache.demand_mshr_hits 0 >> # number of demand (read+write) MSHR hits >> -system.cpu.l2cache.demand_mshr_miss_latency 207200000 >> # number of demand (read+write) MSHR miss cycles >> -system.cpu.l2cache.demand_mshr_miss_rate 0.373441 >> # mshr miss rate for demand accesses >> -system.cpu.l2cache.demand_mshr_misses 5180 >> # number of demand (read+write) MSHR misses >> +system.cpu.l2cache.demand_mshr_miss_latency 206920000 >> # number of demand (read+write) MSHR miss cycles >> +system.cpu.l2cache.demand_mshr_miss_rate 0.373125 >> # mshr miss rate for demand accesses >> +system.cpu.l2cache.demand_mshr_misses 5173 >> # number of demand (read+write) MSHR misses >> system.cpu.l2cache.fast_writes 0 >> # number of fast writes performed >> system.cpu.l2cache.mshr_cap_events 0 >> # number of times MSHR cap was activated >> system.cpu.l2cache.no_allocate_misses 0 >> # Number of misses that were no-allocate >> -system.cpu.l2cache.overall_accesses 13871 >> # number of overall (read+write) accesses >> +system.cpu.l2cache.overall_accesses 13864 >> # number of overall (read+write) accesses >> system.cpu.l2cache.overall_avg_miss_latency 52000 >> # average overall miss latency >> system.cpu.l2cache.overall_avg_mshr_miss_latency 40000 >> # average overall mshr miss latency >> system.cpu.l2cache.overall_avg_mshr_uncacheable_latency <err: div-0> >> # average overall mshr uncacheable latency >> system.cpu.l2cache.overall_hits 8691 >> # number of overall hits >> -system.cpu.l2cache.overall_miss_latency 269360000 >> # number of overall miss cycles >> -system.cpu.l2cache.overall_miss_rate 0.373441 >> # miss rate for overall accesses >> -system.cpu.l2cache.overall_misses 5180 >> # number of overall misses >> +system.cpu.l2cache.overall_miss_latency 268996000 >> # number of overall miss cycles >> +system.cpu.l2cache.overall_miss_rate 0.373125 >> # miss rate for overall accesses >> +system.cpu.l2cache.overall_misses 5173 >> # number of overall misses >> system.cpu.l2cache.overall_mshr_hits 0 >> # number of overall MSHR hits >> -system.cpu.l2cache.overall_mshr_miss_latency 207200000 >> # number of overall MSHR miss cycles >> -system.cpu.l2cache.overall_mshr_miss_rate 0.373441 >> # mshr miss rate for overall accesses >> -system.cpu.l2cache.overall_mshr_misses 5180 >> # number of overall MSHR misses >> +system.cpu.l2cache.overall_mshr_miss_latency 206920000 >> # number of overall MSHR miss cycles >> +system.cpu.l2cache.overall_mshr_miss_rate 0.373125 >> # mshr miss rate for overall accesses >> +system.cpu.l2cache.overall_mshr_misses 5173 >> # number of overall MSHR misses >> system.cpu.l2cache.overall_mshr_uncacheable_latency 0 >> # number of overall MSHR uncacheable cycles >> system.cpu.l2cache.overall_mshr_uncacheable_misses 0 >> # number of overall MSHR uncacheable misses >> system.cpu.l2cache.prefetcher.num_hwpf_already_in_cache 0 >> # number of hwpf that were already in the cache >> @@ -229,14 +229,14 @@ >> system.cpu.l2cache.prefetcher.num_hwpf_span_page 0 >> # number of hwpf spanning a virtual page >> system.cpu.l2cache.prefetcher.num_hwpf_squashed_from_miss 0 >> # number of hwpf that got squashed due to a miss aborting >> calculation time >> system.cpu.l2cache.replacements 0 >> # number of replacements >> -system.cpu.l2cache.sampled_refs 4086 >> # Sample count of references to valid blocks. >> +system.cpu.l2cache.sampled_refs 4072 >> # Sample count of references to valid blocks. >> system.cpu.l2cache.soft_prefetch_mshr_full 0 >> # number of mshr full events for SW prefetching instrutions >> -system.cpu.l2cache.tagsinuse 2657.336317 >> # Cycle average of tags in use >> +system.cpu.l2cache.tagsinuse 2657.329033 >> # Cycle average of tags in use >> system.cpu.l2cache.total_refs 8691 >> # Total number of references to valid blocks. >> system.cpu.l2cache.warmup_cycle 0 >> # Cycle when the warmup percentage was hit. >> system.cpu.l2cache.writebacks 0 >> # number of writebacks >> system.cpu.not_idle_fraction 1 >> # Percentage of non-idle cycles >> -system.cpu.numCycles 541157916 >> # number of cpu cycles simulated >> +system.cpu.numCycles 541157146 >> # number of cpu cycles simulated >> system.cpu.num_insts 193444769 >> # Number of instructions executed >> system.cpu.num_refs 76733959 >> # Number of memory references >> system.cpu.workload.PROG:num_syscalls 401 >> # Number of system calls >> diff -r 7015e400bd1d -r c5447915af50 >> tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout >> --- a/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout Sat Nov 15 >> 23:42:11 2008 -0500 >> +++ b/tests/long/70.twolf/ref/sparc/linux/simple-timing/stdout Mon Nov 17 >> 14:11:09 2008 -0500 >> @@ -5,14 +5,12 @@ >> All Rights Reserved >> >> >> -M5 compiled Nov 5 2008 22:40:47 >> -M5 revision 5719:c9056088f1516d097f7e73673f990175ad238d69 >> -M5 commit date Wed Nov 05 16:19:17 2008 -0500 >> -M5 started Nov 5 2008 22:41:20 >> +M5 compiled Nov 17 2008 13:45:49 >> +M5 revision 5749:7015e400bd1deffa6e51e839baf2ed6d9bd3e31f >> +M5 commit date Sat Nov 15 23:42:11 2008 -0500 >> +M5 started Nov 17 2008 13:46:11 >> M5 executing on zizzer >> command line: build/SPARC_SE/m5.fast -d >> build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing -re >> --stdout-file stdout --stderr-file stderr tests/run.py >> long/70.twolf/sparc/linux/simple-timing >> -Couldn't unlink >> build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sav >> -Couldn't unlink >> build/SPARC_SE/tests/fast/long/70.twolf/sparc/linux/simple-timing/smred.sv2 >> Global frequency set at 1000000000000 ticks per second >> info: Entering event queue @ 0. Starting simulation... >> >> @@ -28,4 +26,4 @@ >> 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 >> 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 >> 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 >> -122 123 124 Exiting @ tick 270578958000 because target called exit() >> +122 123 124 Exiting @ tick 270578573000 because target called exit() >> _______________________________________________ >> m5-dev mailing list >> m5-dev@m5sim.org >> http://m5sim.org/mailman/listinfo/m5-dev >> >> > _______________________________________________ > m5-dev mailing list > m5-dev@m5sim.org > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev
