changeset e5dcc4ca36b0 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=e5dcc4ca36b0
description:
Update the stats for the fixes to the PCI device class.
diffstat:
14 files changed, 133 insertions(+), 249 deletions(-)
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
| 5
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
| 85 ++++------
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/simout
| 5
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3/stats.txt
| 81 ++++-----
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/simout
| 5
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/stats.txt
| 27 ---
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/simout
| 5
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/stats.txt
| 28 +--
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/simout
| 5
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stats.txt
| 59 ++----
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/simout
| 5
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stats.txt
| 62 ++-----
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/simout
| 5
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/stats.txt
| 5
diffs (truncated from 5516 to 300 lines):
diff -r ab2f35347803 -r e5dcc4ca36b0
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Dec
15 00:47:01 2008 -0800
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/simout Mon Dec
15 00:47:15 2008 -0800
@@ -5,12 +5,12 @@
All Rights Reserved
-M5 compiled Dec 4 2008 21:30:58
-M5 revision 5755:d6a5329ec79b40f273fe6dacb70354f281725652
-M5 commit date Thu Dec 04 18:04:32 2008 -0500
-M5 started Dec 4 2008 21:35:52
-M5 executing on zizzer
-command line: build/ALPHA_FS/m5.fast -d
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re
--stdout-file stdout --stderr-file stderr tests/run.py
long/10.linux-boot/alpha/linux/tsunami-o3-dual
+M5 compiled Dec 14 2008 21:47:07
+M5 revision 5776:07905796d7bea4187139808b7de687a99cbc3141
+M5 commit date Sun Dec 14 21:45:15 2008 -0800
+M5 started Dec 14 2008 21:47:53
+M5 executing on tater
+command line: build/ALPHA_FS/m5.fast -d
build/ALPHA_FS/tests/fast/long/10.linux-boot/alpha/linux/tsunami-o3-dual -re
tests/run.py long/10.linux-boot/alpha/linux/tsunami-o3-dual
Global frequency set at 1000000000000 ticks per second
info: Entering event queue @ 0. Starting simulation...
-Exiting @ tick 1907705350500 because m5_exit instruction encountered
+Exiting @ tick 1907705384500 because m5_exit instruction encountered
diff -r ab2f35347803 -r e5dcc4ca36b0
tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
--- a/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Dec 15 00:47:01 2008 -0800
+++ b/tests/long/10.linux-boot/ref/alpha/linux/tsunami-o3-dual/stats.txt
Mon Dec 15 00:47:15 2008 -0800
@@ -2,149 +2,149 @@
---------- Begin Simulation Statistics ----------
global.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
global.BPredUnit.BTBCorrect 0 #
Number of correct BTB predictions (this stat may not work properly.
-global.BPredUnit.BTBHits 4974822 #
Number of BTB hits
-global.BPredUnit.BTBHits 2263931 #
Number of BTB hits
-global.BPredUnit.BTBLookups 9262166 #
Number of BTB lookups
-global.BPredUnit.BTBLookups 5044198 #
Number of BTB lookups
-global.BPredUnit.RASInCorrect 24314 #
Number of incorrect RAS predictions.
-global.BPredUnit.RASInCorrect 16401 #
Number of incorrect RAS predictions.
-global.BPredUnit.condIncorrect 550360 #
Number of conditional branches incorrect
-global.BPredUnit.condIncorrect 327538 #
Number of conditional branches incorrect
-global.BPredUnit.condPredicted 8474519 #
Number of conditional branches predicted
-global.BPredUnit.condPredicted 4548926 #
Number of conditional branches predicted
-global.BPredUnit.lookups 10092697 #
Number of BP lookups
-global.BPredUnit.lookups 5530798 #
Number of BP lookups
-global.BPredUnit.usedRAS 690318 #
Number of times the RAS was used to get a target.
-global.BPredUnit.usedRAS 415111 #
Number of times the RAS was used to get a target.
-host_inst_rate 121094 #
Simulator instruction rate (inst/s)
-host_mem_usage 292872 #
Number of bytes of host memory used
-host_seconds 463.72 #
Real time elapsed on the host
-host_tick_rate 4113887240 #
Simulator tick rate (ticks/s)
-memdepunit.memDep.conflictingLoads 2050196 #
Number of conflicting loads.
-memdepunit.memDep.conflictingLoads 902547 #
Number of conflicting loads.
-memdepunit.memDep.conflictingStores 1831551 #
Number of conflicting stores.
-memdepunit.memDep.conflictingStores 816276 #
Number of conflicting stores.
-memdepunit.memDep.insertedLoads 7552776 #
Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedLoads 4240735 #
Number of loads inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 4835977 #
Number of stores inserted to the mem dependence unit.
-memdepunit.memDep.insertedStores 2555030 #
Number of stores inserted to the mem dependence unit.
+global.BPredUnit.BTBHits 4976196 #
Number of BTB hits
+global.BPredUnit.BTBHits 2271370 #
Number of BTB hits
+global.BPredUnit.BTBLookups 9270308 #
Number of BTB lookups
+global.BPredUnit.BTBLookups 5052293 #
Number of BTB lookups
+global.BPredUnit.RASInCorrect 24350 #
Number of incorrect RAS predictions.
+global.BPredUnit.RASInCorrect 16405 #
Number of incorrect RAS predictions.
+global.BPredUnit.condIncorrect 550496 #
Number of conditional branches incorrect
+global.BPredUnit.condIncorrect 327507 #
Number of conditional branches incorrect
+global.BPredUnit.condPredicted 8475186 #
Number of conditional branches predicted
+global.BPredUnit.condPredicted 4551940 #
Number of conditional branches predicted
+global.BPredUnit.lookups 10093436 #
Number of BP lookups
+global.BPredUnit.lookups 5538388 #
Number of BP lookups
+global.BPredUnit.usedRAS 690374 #
Number of times the RAS was used to get a target.
+global.BPredUnit.usedRAS 417429 #
Number of times the RAS was used to get a target.
+host_inst_rate 132487 #
Simulator instruction rate (inst/s)
+host_mem_usage 294244 #
Number of bytes of host memory used
+host_seconds 424.12 #
Real time elapsed on the host
+host_tick_rate 4498020766 #
Simulator tick rate (ticks/s)
+memdepunit.memDep.conflictingLoads 2050532 #
Number of conflicting loads.
+memdepunit.memDep.conflictingLoads 906322 #
Number of conflicting loads.
+memdepunit.memDep.conflictingStores 1832540 #
Number of conflicting stores.
+memdepunit.memDep.conflictingStores 817104 #
Number of conflicting stores.
+memdepunit.memDep.insertedLoads 7553751 #
Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedLoads 4247428 #
Number of loads inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 4835994 #
Number of stores inserted to the mem dependence unit.
+memdepunit.memDep.insertedStores 2557361 #
Number of stores inserted to the mem dependence unit.
sim_freq 1000000000000 #
Frequency of simulated ticks
-sim_insts 56154063 #
Number of instructions simulated
+sim_insts 56190549 #
Number of instructions simulated
sim_seconds 1.907705 #
Number of seconds simulated
-sim_ticks 1907705350500 #
Number of ticks simulated
-system.cpu0.commit.COM:branches 5979955 #
Number of branches committed
-system.cpu0.commit.COM:bw_lim_events 670629 #
number cycles where commit BW limit reached
+sim_ticks 1907705384500 #
Number of ticks simulated
+system.cpu0.commit.COM:branches 5979895 #
Number of branches committed
+system.cpu0.commit.COM:bw_lim_events 670394 #
number cycles where commit BW limit reached
system.cpu0.commit.COM:bw_limited 0 #
number of insts not committed due to BW limits
system.cpu0.commit.COM:committed_per_cycle.start_dist #
Number of insts commited each cycle
-system.cpu0.commit.COM:committed_per_cycle.samples 69429521
+system.cpu0.commit.COM:committed_per_cycle.samples 69432721
system.cpu0.commit.COM:committed_per_cycle.min_value 0
- 0 52132882 7508.75%
- 1 7659816 1103.25%
- 2 4444319 640.12%
- 3 2023012 291.38%
- 4 1474688 212.40%
- 5 453462 65.31%
- 6 276660 39.85%
- 7 294053 42.35%
- 8 670629 96.59%
+ 0 52134013 7508.57%
+ 1 7662361 1103.57%
+ 2 4443978 640.04%
+ 3 2023859 291.48%
+ 4 1473823 212.27%
+ 5 453847 65.37%
+ 6 276435 39.81%
+ 7 294011 42.34%
+ 8 670394 96.55%
system.cpu0.commit.COM:committed_per_cycle.max_value 8
system.cpu0.commit.COM:committed_per_cycle.end_dist
-system.cpu0.commit.COM:count 39866915 #
Number of instructions committed
-system.cpu0.commit.COM:loads 6404567 #
Number of loads committed
-system.cpu0.commit.COM:membars 151031 #
Number of memory barriers committed
-system.cpu0.commit.COM:refs 10831807 #
Number of memory references committed
+system.cpu0.commit.COM:count 39866260 #
Number of instructions committed
+system.cpu0.commit.COM:loads 6404474 #
Number of loads committed
+system.cpu0.commit.COM:membars 151021 #
Number of memory barriers committed
+system.cpu0.commit.COM:refs 10831640 #
Number of memory references committed
system.cpu0.commit.COM:swp_count 0 #
Number of s/w prefetches committed
-system.cpu0.commit.branchMispredicts 524319 #
The number of times a branch was mispredicted
-system.cpu0.commit.commitCommittedInsts 39866915 #
The number of committed instructions
-system.cpu0.commit.commitNonSpecStalls 458411 #
The number of times commit has been forced to stall to communicate backwards
-system.cpu0.commit.commitSquashedInsts 6215021 #
The number of squashed insts skipped by commit
-system.cpu0.committedInsts 37661300 #
Number of Instructions Simulated
-system.cpu0.committedInsts_total 37661300 #
Number of Instructions Simulated
-system.cpu0.cpi 2.679168 #
CPI: Cycles Per Instruction
-system.cpu0.cpi_total 2.679168 #
CPI: Total CPI of All Threads
-system.cpu0.dcache.LoadLockedReq_accesses 147705 #
number of LoadLockedReq accesses(hits+misses)
-system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15410.210138
# average LoadLockedReq miss latency
-system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11873.163354
# average LoadLockedReq mshr miss latency
-system.cpu0.dcache.LoadLockedReq_hits 135237 #
number of LoadLockedReq hits
-system.cpu0.dcache.LoadLockedReq_miss_latency 192134500
# number of LoadLockedReq miss cycles
-system.cpu0.dcache.LoadLockedReq_miss_rate 0.084411
# miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_misses 12468 #
number of LoadLockedReq misses
-system.cpu0.dcache.LoadLockedReq_mshr_hits 3212
# number of LoadLockedReq MSHR hits
-system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109898000
# number of LoadLockedReq MSHR miss cycles
-system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062665
# mshr miss rate for LoadLockedReq accesses
-system.cpu0.dcache.LoadLockedReq_mshr_misses 9256
# number of LoadLockedReq MSHR misses
-system.cpu0.dcache.ReadReq_accesses 6414335 #
number of ReadReq accesses(hits+misses)
-system.cpu0.dcache.ReadReq_avg_miss_latency 28975.310559
# average ReadReq miss latency
-system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28717.266435
# average ReadReq mshr miss latency
+system.cpu0.commit.branchMispredicts 524450 #
The number of times a branch was mispredicted
+system.cpu0.commit.commitCommittedInsts 39866260 #
The number of committed instructions
+system.cpu0.commit.commitNonSpecStalls 458375 #
The number of times commit has been forced to stall to communicate backwards
+system.cpu0.commit.commitSquashedInsts 6218747 #
The number of squashed insts skipped by commit
+system.cpu0.committedInsts 37660679 #
Number of Instructions Simulated
+system.cpu0.committedInsts_total 37660679 #
Number of Instructions Simulated
+system.cpu0.cpi 2.679241 #
CPI: Cycles Per Instruction
+system.cpu0.cpi_total 2.679241 #
CPI: Total CPI of All Threads
+system.cpu0.dcache.LoadLockedReq_accesses 147686 #
number of LoadLockedReq accesses(hits+misses)
+system.cpu0.dcache.LoadLockedReq_avg_miss_latency 15414.654688
# average LoadLockedReq miss latency
+system.cpu0.dcache.LoadLockedReq_avg_mshr_miss_latency 11879.766663
# average LoadLockedReq mshr miss latency
+system.cpu0.dcache.LoadLockedReq_hits 135219 #
number of LoadLockedReq hits
+system.cpu0.dcache.LoadLockedReq_miss_latency 192174500
# number of LoadLockedReq miss cycles
+system.cpu0.dcache.LoadLockedReq_miss_rate 0.084416
# miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_misses 12467 #
number of LoadLockedReq misses
+system.cpu0.dcache.LoadLockedReq_mshr_hits 3210
# number of LoadLockedReq MSHR hits
+system.cpu0.dcache.LoadLockedReq_mshr_miss_latency 109971000
# number of LoadLockedReq MSHR miss cycles
+system.cpu0.dcache.LoadLockedReq_mshr_miss_rate 0.062680
# mshr miss rate for LoadLockedReq accesses
+system.cpu0.dcache.LoadLockedReq_mshr_misses 9257
# number of LoadLockedReq MSHR misses
+system.cpu0.dcache.ReadReq_accesses 6414696 #
number of ReadReq accesses(hits+misses)
+system.cpu0.dcache.ReadReq_avg_miss_latency 28975.378056
# average ReadReq miss latency
+system.cpu0.dcache.ReadReq_avg_mshr_miss_latency 28716.351233
# average ReadReq mshr miss latency
system.cpu0.dcache.ReadReq_avg_mshr_uncacheable_latency inf
# average ReadReq mshr uncacheable latency
-system.cpu0.dcache.ReadReq_hits 5467655 #
number of ReadReq hits
-system.cpu0.dcache.ReadReq_miss_latency 27430347000 #
number of ReadReq miss cycles
-system.cpu0.dcache.ReadReq_miss_rate 0.147588 #
miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_misses 946680 #
number of ReadReq misses
-system.cpu0.dcache.ReadReq_mshr_hits 250995 #
number of ReadReq MSHR hits
-system.cpu0.dcache.ReadReq_mshr_miss_latency 19978171500
# number of ReadReq MSHR miss cycles
-system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108458 #
mshr miss rate for ReadReq accesses
-system.cpu0.dcache.ReadReq_mshr_misses 695685 #
number of ReadReq MSHR misses
-system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639869500
# number of ReadReq MSHR uncacheable cycles
-system.cpu0.dcache.StoreCondReq_accesses 156562 #
number of StoreCondReq accesses(hits+misses)
-system.cpu0.dcache.StoreCondReq_avg_miss_latency 54665.657574
# average StoreCondReq miss latency
-system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51665.657574
# average StoreCondReq mshr miss latency
-system.cpu0.dcache.StoreCondReq_hits 140541 #
number of StoreCondReq hits
-system.cpu0.dcache.StoreCondReq_miss_latency 875798500
# number of StoreCondReq miss cycles
-system.cpu0.dcache.StoreCondReq_miss_rate 0.102330 #
miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_misses 16021 #
number of StoreCondReq misses
-system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827735500
# number of StoreCondReq MSHR miss cycles
-system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102330
# mshr miss rate for StoreCondReq accesses
-system.cpu0.dcache.StoreCondReq_mshr_misses 16021
# number of StoreCondReq MSHR misses
-system.cpu0.dcache.WriteReq_accesses 4258124 #
number of WriteReq accesses(hits+misses)
-system.cpu0.dcache.WriteReq_avg_miss_latency 48857.609779
# average WriteReq miss latency
-system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53932.670870
# average WriteReq mshr miss latency
+system.cpu0.dcache.ReadReq_hits 5468142 #
number of ReadReq hits
+system.cpu0.dcache.ReadReq_miss_latency 27426760000 #
number of ReadReq miss cycles
+system.cpu0.dcache.ReadReq_miss_rate 0.147560 #
miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_misses 946554 #
number of ReadReq misses
+system.cpu0.dcache.ReadReq_mshr_hits 250845 #
number of ReadReq MSHR hits
+system.cpu0.dcache.ReadReq_mshr_miss_latency 19978224000
# number of ReadReq MSHR miss cycles
+system.cpu0.dcache.ReadReq_mshr_miss_rate 0.108455 #
mshr miss rate for ReadReq accesses
+system.cpu0.dcache.ReadReq_mshr_misses 695709 #
number of ReadReq MSHR misses
+system.cpu0.dcache.ReadReq_mshr_uncacheable_latency 639862500
# number of ReadReq MSHR uncacheable cycles
+system.cpu0.dcache.StoreCondReq_accesses 156551 #
number of StoreCondReq accesses(hits+misses)
+system.cpu0.dcache.StoreCondReq_avg_miss_latency 54667.977283
# average StoreCondReq miss latency
+system.cpu0.dcache.StoreCondReq_avg_mshr_miss_latency 51667.977283
# average StoreCondReq mshr miss latency
+system.cpu0.dcache.StoreCondReq_hits 140528 #
number of StoreCondReq hits
+system.cpu0.dcache.StoreCondReq_miss_latency 875945000
# number of StoreCondReq miss cycles
+system.cpu0.dcache.StoreCondReq_miss_rate 0.102350 #
miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_misses 16023 #
number of StoreCondReq misses
+system.cpu0.dcache.StoreCondReq_mshr_miss_latency 827876000
# number of StoreCondReq MSHR miss cycles
+system.cpu0.dcache.StoreCondReq_mshr_miss_rate 0.102350
# mshr miss rate for StoreCondReq accesses
+system.cpu0.dcache.StoreCondReq_mshr_misses 16023
# number of StoreCondReq MSHR misses
+system.cpu0.dcache.WriteReq_accesses 4258061 #
number of WriteReq accesses(hits+misses)
+system.cpu0.dcache.WriteReq_avg_miss_latency 48857.574152
# average WriteReq miss latency
+system.cpu0.dcache.WriteReq_avg_mshr_miss_latency 53930.516019
# average WriteReq mshr miss latency
system.cpu0.dcache.WriteReq_avg_mshr_uncacheable_latency inf
# average WriteReq mshr uncacheable latency
-system.cpu0.dcache.WriteReq_hits 2612795 #
number of WriteReq hits
-system.cpu0.dcache.WriteReq_miss_latency 80386842240 #
number of WriteReq miss cycles
-system.cpu0.dcache.WriteReq_miss_rate 0.386398 #
miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_misses 1645329 #
number of WriteReq misses
-system.cpu0.dcache.WriteReq_mshr_hits 1362201 #
number of WriteReq MSHR hits
-system.cpu0.dcache.WriteReq_mshr_miss_latency 15269849238
# number of WriteReq MSHR miss cycles
-system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066491
# mshr miss rate for WriteReq accesses
-system.cpu0.dcache.WriteReq_mshr_misses 283128 #
number of WriteReq MSHR misses
-system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050385997
# number of WriteReq MSHR uncacheable cycles
-system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9304.837348
# average number of cycles each access was blocked
+system.cpu0.dcache.WriteReq_hits 2612712 #
number of WriteReq hits
+system.cpu0.dcache.WriteReq_miss_latency 80387760774 #
number of WriteReq miss cycles
+system.cpu0.dcache.WriteReq_miss_rate 0.386408 #
miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_misses 1645349 #
number of WriteReq misses
+system.cpu0.dcache.WriteReq_mshr_hits 1362208 #
number of WriteReq MSHR hits
+system.cpu0.dcache.WriteReq_mshr_miss_latency 15269940236
# number of WriteReq MSHR miss cycles
+system.cpu0.dcache.WriteReq_mshr_miss_rate 0.066495
# mshr miss rate for WriteReq accesses
+system.cpu0.dcache.WriteReq_mshr_misses 283141 #
number of WriteReq MSHR misses
+system.cpu0.dcache.WriteReq_mshr_uncacheable_latency 1050786497
# number of WriteReq MSHR uncacheable cycles
+system.cpu0.dcache.avg_blocked_cycles_no_mshrs 9307.072518
# average number of cycles each access was blocked
system.cpu0.dcache.avg_blocked_cycles_no_targets 16250
# average number of cycles each access was blocked
-system.cpu0.dcache.avg_refs 9.224078 #
Average number of references to valid blocks.
-system.cpu0.dcache.blocked_no_mshrs 116353 #
number of cycles access was blocked
+system.cpu0.dcache.avg_refs 9.224260 #
Average number of references to valid blocks.
+system.cpu0.dcache.blocked_no_mshrs 116343 #
number of cycles access was blocked
system.cpu0.dcache.blocked_no_targets 2 #
number of cycles access was blocked
-system.cpu0.dcache.blocked_cycles_no_mshrs 1082645740
# number of cycles access was blocked
+system.cpu0.dcache.blocked_cycles_no_mshrs 1082812738
# number of cycles access was blocked
system.cpu0.dcache.blocked_cycles_no_targets 32500
# number of cycles access was blocked
system.cpu0.dcache.cache_copies 0 #
number of cache copies performed
-system.cpu0.dcache.demand_accesses 10672459 #
number of demand (read+write) accesses
-system.cpu0.dcache.demand_avg_miss_latency 41595.993394
# average overall miss latency
-system.cpu0.dcache.demand_avg_mshr_miss_latency 36010.985488
# average overall mshr miss latency
-system.cpu0.dcache.demand_hits 8080450 #
number of demand (read+write) hits
-system.cpu0.dcache.demand_miss_latency 107817189240 #
number of demand (read+write) miss cycles
-system.cpu0.dcache.demand_miss_rate 0.242869 #
miss rate for demand accesses
-system.cpu0.dcache.demand_misses 2592009 #
number of demand (read+write) misses
-system.cpu0.dcache.demand_mshr_hits 1613196 #
number of demand (read+write) MSHR hits
-system.cpu0.dcache.demand_mshr_miss_latency 35248020738
# number of demand (read+write) MSHR miss cycles
-system.cpu0.dcache.demand_mshr_miss_rate 0.091714 #
mshr miss rate for demand accesses
-system.cpu0.dcache.demand_mshr_misses 978813 #
number of demand (read+write) MSHR misses
+system.cpu0.dcache.demand_accesses 10672757 #
number of demand (read+write) accesses
+system.cpu0.dcache.demand_avg_miss_latency 41596.664989
# average overall miss latency
+system.cpu0.dcache.demand_avg_mshr_miss_latency 36009.770890
# average overall mshr miss latency
+system.cpu0.dcache.demand_hits 8080854 #
number of demand (read+write) hits
+system.cpu0.dcache.demand_miss_latency 107814520774 #
number of demand (read+write) miss cycles
+system.cpu0.dcache.demand_miss_rate 0.242852 #
miss rate for demand accesses
+system.cpu0.dcache.demand_misses 2591903 #
number of demand (read+write) misses
+system.cpu0.dcache.demand_mshr_hits 1613053 #
number of demand (read+write) MSHR hits
+system.cpu0.dcache.demand_mshr_miss_latency 35248164236
# number of demand (read+write) MSHR miss cycles
+system.cpu0.dcache.demand_mshr_miss_rate 0.091715 #
mshr miss rate for demand accesses
+system.cpu0.dcache.demand_mshr_misses 978850 #
number of demand (read+write) MSHR misses
system.cpu0.dcache.fast_writes 0 #
number of fast writes performed
system.cpu0.dcache.mshr_cap_events 0 #
number of times MSHR cap was activated
system.cpu0.dcache.no_allocate_misses 0 #
Number of misses that were no-allocate
-system.cpu0.dcache.overall_accesses 10672459 #
number of overall (read+write) accesses
-system.cpu0.dcache.overall_avg_miss_latency 41595.993394
# average overall miss latency
-system.cpu0.dcache.overall_avg_mshr_miss_latency 36010.985488
# average overall mshr miss latency
+system.cpu0.dcache.overall_accesses 10672757 #
number of overall (read+write) accesses
+system.cpu0.dcache.overall_avg_miss_latency 41596.664989
# average overall miss latency
+system.cpu0.dcache.overall_avg_mshr_miss_latency 36009.770890
# average overall mshr miss latency
system.cpu0.dcache.overall_avg_mshr_uncacheable_latency inf
# average overall mshr uncacheable latency
-system.cpu0.dcache.overall_hits 8080450 #
number of overall hits
-system.cpu0.dcache.overall_miss_latency 107817189240 #
number of overall miss cycles
-system.cpu0.dcache.overall_miss_rate 0.242869 #
miss rate for overall accesses
-system.cpu0.dcache.overall_misses 2592009 #
number of overall misses
-system.cpu0.dcache.overall_mshr_hits 1613196 #
number of overall MSHR hits
-system.cpu0.dcache.overall_mshr_miss_latency 35248020738
# number of overall MSHR miss cycles
-system.cpu0.dcache.overall_mshr_miss_rate 0.091714 #
mshr miss rate for overall accesses
-system.cpu0.dcache.overall_mshr_misses 978813 #
number of overall MSHR misses
-system.cpu0.dcache.overall_mshr_uncacheable_latency 1690255497
# number of overall MSHR uncacheable cycles
+system.cpu0.dcache.overall_hits 8080854 #
number of overall hits
+system.cpu0.dcache.overall_miss_latency 107814520774 #
number of overall miss cycles
+system.cpu0.dcache.overall_miss_rate 0.242852 #
miss rate for overall accesses
+system.cpu0.dcache.overall_misses 2591903 #
number of overall misses
+system.cpu0.dcache.overall_mshr_hits 1613053 #
number of overall MSHR hits
+system.cpu0.dcache.overall_mshr_miss_latency 35248164236
# number of overall MSHR miss cycles
+system.cpu0.dcache.overall_mshr_miss_rate 0.091715 #
mshr miss rate for overall accesses
+system.cpu0.dcache.overall_mshr_misses 978850 #
number of overall MSHR misses
+system.cpu0.dcache.overall_mshr_uncacheable_latency 1690648997
# number of overall MSHR uncacheable cycles
system.cpu0.dcache.overall_mshr_uncacheable_misses 0
# number of overall MSHR uncacheable misses
system.cpu0.dcache.prefetcher.num_hwpf_already_in_cache 0
# number of hwpf that were already in the cache
system.cpu0.dcache.prefetcher.num_hwpf_already_in_mshr 0
# number of hwpf that were already in mshr
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
