changeset c0d731772342 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=c0d731772342
description:
SPARC: Truncate syscall args and return values appropriately.
diffstat:
2 files changed, 9 insertions(+), 3 deletions(-)
src/arch/sparc/syscallreturn.hh | 7 ++++++-
src/cpu/simple_thread.hh | 5 +++--
diffs (50 lines):
diff -r e5dcc4ca36b0 -r c0d731772342 src/arch/sparc/syscallreturn.hh
--- a/src/arch/sparc/syscallreturn.hh Mon Dec 15 00:47:15 2008 -0800
+++ b/src/arch/sparc/syscallreturn.hh Tue Dec 16 23:06:37 2008 -0800
@@ -50,13 +50,23 @@
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) & 0xEE);
//tc->setMiscRegNoEffect(MISCREG_CCR,
tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
- tc->setIntReg(ReturnValueReg, return_value.value());
+ IntReg val = return_value.value();
+ if (bits(tc->readMiscRegNoEffect(
+ SparcISA::MISCREG_PSTATE), 3, 3)) {
+ val = bits(val, 31, 0);
+ }
+ tc->setIntReg(ReturnValueReg, val);
} else {
// got an error, set XCC.C
tc->setIntReg(NumIntArchRegs + 2,
tc->readIntReg(NumIntArchRegs + 2) | 0x11);
//tc->setMiscRegNoEffect(MISCREG_CCR,
tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
- tc->setIntReg(ReturnValueReg, -return_value.value());
+ IntReg val = -return_value.value();
+ if (bits(tc->readMiscRegNoEffect(
+ SparcISA::MISCREG_PSTATE), 3, 3)) {
+ val = bits(val, 31, 0);
+ }
+ tc->setIntReg(ReturnValueReg, val);
}
}
};
diff -r e5dcc4ca36b0 -r c0d731772342 src/cpu/simple_thread.hh
--- a/src/cpu/simple_thread.hh Mon Dec 15 00:47:15 2008 -0800
+++ b/src/cpu/simple_thread.hh Tue Dec 16 23:06:37 2008 -0800
@@ -385,8 +385,15 @@
TheISA::IntReg getSyscallArg(int i)
{
assert(i < TheISA::NumArgumentRegs);
- return regs.readIntReg(TheISA::flattenIntIndex(getTC(),
- TheISA::ArgumentReg[i]));
+ TheISA::IntReg val = regs.readIntReg(
+ TheISA::flattenIntIndex(getTC(), TheISA::ArgumentReg[i]));
+#if THE_ISA == SPARC_ISA
+ if (bits(this->readMiscRegNoEffect(
+ SparcISA::MISCREG_PSTATE), 3, 3)) {
+ val = bits(val, 31, 0);
+ }
+#endif
+ return val;
}
// used to shift args for indirect syscall
_______________________________________________
m5-dev mailing list
[email protected]
http://m5sim.org/mailman/listinfo/m5-dev
