changeset 54ed46881217 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=54ed46881217 description: CPU: Prepare CPU models for the new in-order CPU model. Some new functions and forward declarations are necessary to make things work
diffstat: 3 files changed, 17 insertions(+), 7 deletions(-) src/cpu/SConscript | 10 ++++++---- src/cpu/o3/ras.hh | 3 +++ src/cpu/static_inst.hh | 11 ++++++++--- diffs (71 lines): diff -r 780dd1bead5c -r 54ed46881217 src/cpu/SConscript --- a/src/cpu/SConscript Mon Feb 09 20:10:15 2009 -0800 +++ b/src/cpu/SConscript Tue Feb 10 15:49:29 2009 -0800 @@ -48,12 +48,14 @@ # Template for execute() signature. exec_sig_template = ''' -virtual Fault execute(%s *xc, Trace::InstRecord *traceData) const = 0; -virtual Fault initiateAcc(%s *xc, Trace::InstRecord *traceData) const +virtual Fault execute(%(type)s *xc, Trace::InstRecord *traceData) const = 0; +virtual Fault initiateAcc(%(type)s *xc, Trace::InstRecord *traceData) const { panic("initiateAcc not defined!"); M5_DUMMY_RETURN }; -virtual Fault completeAcc(Packet *pkt, %s *xc, +virtual Fault completeAcc(Packet *pkt, %(type)s *xc, Trace::InstRecord *traceData) const { panic("completeAcc not defined!"); M5_DUMMY_RETURN }; +virtual int memAccSize(%(type)s *xc) +{ panic("memAccSize not defined!"); M5_DUMMY_RETURN }; ''' mem_ini_sig_template = ''' @@ -82,7 +84,7 @@ ''' for cpu in temp_cpu_list: xc_type = CpuModel.dict[cpu].strings['CPU_exec_context'] - print >> f, exec_sig_template % (xc_type, xc_type, xc_type) + print >> f, exec_sig_template % { 'type' : xc_type } print >> f, ''' #endif // __CPU_STATIC_INST_EXEC_SIGS_HH__ ''' diff -r 780dd1bead5c -r 54ed46881217 src/cpu/o3/ras.hh --- a/src/cpu/o3/ras.hh Mon Feb 09 20:10:15 2009 -0800 +++ b/src/cpu/o3/ras.hh Tue Feb 10 15:49:29 2009 -0800 @@ -71,6 +71,9 @@ */ void restore(unsigned top_entry_idx, const Addr &restored_target); + bool empty() { return usedEntries == 0; } + + bool full() { return usedEntries == numEntries; } private: /** Increments the top of stack index. */ inline void incrTos() diff -r 780dd1bead5c -r 54ed46881217 src/cpu/static_inst.hh --- a/src/cpu/static_inst.hh Mon Feb 09 20:10:15 2009 -0800 +++ b/src/cpu/static_inst.hh Tue Feb 10 15:49:29 2009 -0800 @@ -56,9 +56,8 @@ class O3CPUImpl; template <class Impl> class BaseO3DynInst; typedef BaseO3DynInst<O3CPUImpl> O3DynInst; - -template <class Impl> -class OzoneDynInst; +template <class Impl> class OzoneDynInst; +class InOrderDynInst; class CheckerCPU; class FastCPU; @@ -434,6 +433,12 @@ */ bool hasBranchTarget(Addr pc, ThreadContext *tc, Addr &tgt) const; + virtual Request::Flags memAccFlags() + { + panic("StaticInst::memAccFlags called on non-memory instruction"); + return 0; + }; + /** * Return string representation of disassembled instruction. * The default version of this function will call the internal _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev