changeset d82be3235ab4 in /z/repo/m5
details: http://repo.m5sim.org/m5?cmd=changeset;node=d82be3235ab4
description:
Fixes to get prefetching working again.
Apparently we broke it with the cache rewrite and never noticed.
Thanks to Bao Yungang <[email protected]> for a significant part
of these changes (and for inspiring me to work on the rest).
Some other overdue cleanup on the prefetch code too.
diffstat:
18 files changed, 383 insertions(+), 348 deletions(-)
src/cpu/base.cc | 6 +
src/mem/cache/BaseCache.py | 12 +-
src/mem/cache/base.hh | 15 +--
src/mem/cache/blk.hh | 2
src/mem/cache/builder.cc | 92 ++++----------------
src/mem/cache/cache.hh | 12 ++
src/mem/cache/cache_impl.hh | 91 ++++++++++++++------
src/mem/cache/mshr.cc | 34 +++++--
src/mem/cache/mshr.hh | 19 ++--
src/mem/cache/prefetch/base.cc | 168 +++++++++++++++++++++-----------------
src/mem/cache/prefetch/base.hh | 24 ++++-
src/mem/cache/prefetch/ghb.cc | 35 +++----
src/mem/cache/prefetch/ghb.hh | 6 -
src/mem/cache/prefetch/stride.cc | 119 +++++++++++++++++---------
src/mem/cache/prefetch/stride.hh | 30 +++---
src/mem/cache/prefetch/tagged.cc | 19 +---
src/mem/config/prefetch.hh | 41 ---------
src/mem/request.hh | 6 +
diffs (truncated from 1271 to 300 lines):
diff -r 7a74edaa8741 -r d82be3235ab4 src/cpu/base.cc
--- a/src/cpu/base.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/cpu/base.cc Mon Feb 16 08:56:40 2009 -0800
@@ -344,8 +344,12 @@
assert(newTC->threadId() == oldTC->threadId());
system->replaceThreadContext(newTC, newTC->contextId());
- if (DTRACE(Context))
+ /* This code no longer works since the zero register (e.g.,
+ * r31 on Alpha) doesn't necessarily contain zero at this
+ * point.
+ if (DTRACE(Context))
ThreadContext::compare(oldTC, newTC);
+ */
}
#if FULL_SYSTEM
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/BaseCache.py
--- a/src/mem/cache/BaseCache.py Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/BaseCache.py Mon Feb 16 08:56:40 2009 -0800
@@ -52,12 +52,10 @@
two_queue = Param.Bool(False,
"whether the lifo should have two queue replacement")
write_buffers = Param.Int(8, "number of write buffers")
- prefetch_miss = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Miss stream")
- prefetch_access = Param.Bool(False,
- "wheter you are using the hardware prefetcher from Access stream")
+ prefetch_on_access = Param.Bool(False,
+ "notify the hardware prefetcher on every access (not just misses)")
prefetcher_size = Param.Int(100,
- "Number of entries in the harware prefetch queue")
+ "Number of entries in the hardware prefetch queue")
prefetch_past_page = Param.Bool(False,
"Allow prefetches to cross virtual page boundaries")
prefetch_serial_squash = Param.Bool(False,
@@ -69,9 +67,9 @@
prefetch_policy = Param.Prefetch('none',
"Type of prefetcher to use")
prefetch_cache_check_push = Param.Bool(True,
- "Check if in cash on push or pop of prefetch queue")
+ "Check if in cache on push or pop of prefetch queue")
prefetch_use_cpu_id = Param.Bool(True,
- "Use the CPU ID to seperate calculations of prefetches")
+ "Use the CPU ID to separate calculations of prefetches")
prefetch_data_accesses_only = Param.Bool(False,
"Only prefetch on data not on instruction accesses")
cpu_side = Port("Port on side closer to CPU")
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/base.hh
--- a/src/mem/cache/base.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/base.hh Mon Feb 16 08:56:40 2009 -0800
@@ -445,12 +445,6 @@
}
}
- Tick nextMSHRReadyTime()
- {
- return std::min(mshrQueue.nextMSHRReadyTime(),
- writeBuffer.nextMSHRReadyTime());
- }
-
/**
* Request the master bus for the given cause and time.
* @param cause The reason for the request.
@@ -467,10 +461,11 @@
*/
void deassertMemSideBusRequest(RequestCause cause)
{
- // obsolete!!
- assert(false);
- // memSidePort->deassertBusRequest(cause);
- // checkDrain();
+ // Obsolete... we no longer signal bus requests explicitly so
+ // we can't deassert them. Leaving this in as a no-op since
+ // the prefetcher calls it to indicate that it no longer wants
+ // to request a prefetch, and someday that might be
+ // interesting again.
}
virtual unsigned int drain(Event *de);
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/blk.hh
--- a/src/mem/cache/blk.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/blk.hh Mon Feb 16 08:56:40 2009 -0800
@@ -205,7 +205,7 @@
* be touched.
* @return True if the block was a hardware prefetch, unaccesed.
*/
- bool isPrefetch() const
+ bool wasPrefetched() const
{
return (status & BlkHWPrefetched) != 0;
}
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/builder.cc
--- a/src/mem/cache/builder.cc Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/builder.cc Mon Feb 16 08:56:40 2009 -0800
@@ -38,7 +38,6 @@
// Must be included first to determine which caches we want
#include "enums/Prefetch.hh"
#include "mem/config/cache.hh"
-#include "mem/config/prefetch.hh"
#include "mem/cache/base.hh"
#include "mem/cache/cache.hh"
#include "mem/bus.hh"
@@ -58,38 +57,32 @@
#endif
//Prefetcher Headers
-#if defined(USE_GHB)
#include "mem/cache/prefetch/ghb.hh"
-#endif
-#if defined(USE_TAGGED)
#include "mem/cache/prefetch/tagged.hh"
-#endif
-#if defined(USE_STRIDED)
#include "mem/cache/prefetch/stride.hh"
-#endif
using namespace std;
using namespace TheISA;
-#define BUILD_CACHE(TAGS, tags) \
- do { \
- BasePrefetcher *pf; \
- if (prefetch_policy == Enums::tagged) { \
- BUILD_TAGGED_PREFETCHER(TAGS); \
- } \
- else if (prefetch_policy == Enums::stride) { \
- BUILD_STRIDED_PREFETCHER(TAGS); \
- } \
- else if (prefetch_policy == Enums::ghb) { \
- BUILD_GHB_PREFETCHER(TAGS); \
- } \
- else { \
- BUILD_NULL_PREFETCHER(TAGS); \
- } \
- Cache<TAGS> *retval = \
- new Cache<TAGS>(this, tags, pf); \
- return retval; \
+#define BUILD_CACHE(TAGS, tags) \
+ do { \
+ BasePrefetcher *pf; \
+ if (prefetch_policy == Enums::tagged) { \
+ pf = new TaggedPrefetcher(this); \
+ } \
+ else if (prefetch_policy == Enums::stride) { \
+ pf = new StridePrefetcher(this); \
+ } \
+ else if (prefetch_policy == Enums::ghb) { \
+ pf = new GHBPrefetcher(this); \
+ } \
+ else { \
+ pf = NULL; \
+ } \
+ Cache<TAGS> *retval = \
+ new Cache<TAGS>(this, tags, pf); \
+ return retval; \
} while (0)
#define BUILD_CACHE_PANIC(x) do { \
@@ -135,37 +128,6 @@
} \
} while (0)
-#define BUILD_COHERENCE(b) do { \
- } while (0)
-
-#if defined(USE_TAGGED)
-#define BUILD_TAGGED_PREFETCHER(t) \
- pf = new TaggedPrefetcher(this)
-#else
-#define BUILD_TAGGED_PREFETCHER(t) BUILD_CACHE_PANIC("Tagged Prefetcher")
-#endif
-
-#if defined(USE_STRIDED)
-#define BUILD_STRIDED_PREFETCHER(t) \
- pf = new StridePrefetcher(this)
-#else
-#define BUILD_STRIDED_PREFETCHER(t) BUILD_CACHE_PANIC("Stride Prefetcher")
-#endif
-
-#if defined(USE_GHB)
-#define BUILD_GHB_PREFETCHER(t) \
- pf = new GHBPrefetcher(this)
-#else
-#define BUILD_GHB_PREFETCHER(t) BUILD_CACHE_PANIC("GHB Prefetcher")
-#endif
-
-#if defined(USE_TAGGED)
-#define BUILD_NULL_PREFETCHER(t) \
- pf = new TaggedPrefetcher(this)
-#else
-#define BUILD_NULL_PREFETCHER(t) BUILD_CACHE_PANIC("NULL Prefetcher (uses
Tagged)")
-#endif
-
BaseCache *
BaseCacheParams::create()
{
@@ -174,24 +136,6 @@
subblock_size = block_size;
}
- //Warnings about prefetcher policy
- if (prefetch_policy == Enums::none) {
- if (prefetch_miss || prefetch_access)
- panic("With no prefetcher, you shouldn't prefetch from"
- " either miss or access stream\n");
- }
-
- if (prefetch_policy == Enums::tagged || prefetch_policy == Enums::stride ||
- prefetch_policy == Enums::ghb) {
-
- if (!prefetch_miss && !prefetch_access)
- warn("With this prefetcher you should chose a prefetch"
- " stream (miss or access)\nNo Prefetching will occur\n");
-
- if (prefetch_miss && prefetch_access)
- panic("Can't do prefetches from both miss and access stream");
- }
-
#if defined(USE_CACHE_IIC)
// Build IIC params
IIC::Params iic_params;
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/cache.hh
--- a/src/mem/cache/cache.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/cache.hh Mon Feb 16 08:56:40 2009 -0800
@@ -64,8 +64,6 @@
/** A typedef for a list of BlkType pointers. */
typedef typename TagStore::BlkList BlkList;
- bool prefetchAccess;
-
protected:
class CpuSidePort : public CachePort
@@ -141,7 +139,10 @@
*/
const bool doFastWrites;
- const bool prefetchMiss;
+ /**
+ * Notify the prefetcher on every access, not just misses.
+ */
+ const bool prefetchOnAccess;
/**
* Does all the processing necessary to perform the provided request.
@@ -320,6 +321,11 @@
bool inMissQueue(Addr addr) {
return (mshrQueue.findMatch(addr) != 0);
}
+
+ /**
+ * Find next request ready time from among possible sources.
+ */
+ Tick nextMSHRReadyTime();
};
#endif // __CACHE_HH__
diff -r 7a74edaa8741 -r d82be3235ab4 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh Sun Feb 15 23:43:39 2009 -0800
+++ b/src/mem/cache/cache_impl.hh Mon Feb 16 08:56:40 2009 -0800
@@ -53,11 +53,10 @@
template<class TagStore>
Cache<TagStore>::Cache(const Params *p, TagStore *tags, BasePrefetcher *pf)
: BaseCache(p),
- prefetchAccess(p->prefetch_access),
tags(tags),
prefetcher(pf),
doFastWrites(true),
- prefetchMiss(p->prefetch_miss)
+ prefetchOnAccess(p->prefetch_on_access)
{
tempBlock = new BlkType();
tempBlock->data = new uint8_t[blkSize];
@@ -72,7 +71,8 @@
memSidePort->setOtherPort(cpuSidePort);
tags->setCache(this);
- prefetcher->setCache(this);
+ if (prefetcher)
+ prefetcher->setCache(this);
}
template<class TagStore>
@@ -81,7 +81,8 @@
{
BaseCache::regStats();
tags->regStats(name());
- prefetcher->regStats(name());
+ if (prefetcher)
+ prefetcher->regStats(name());
}
template<class TagStore>
@@ -271,29 +272,11 @@
blk = tags->accessBlock(pkt->getAddr(), lat);
- if (prefetchAccess) {
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