Comments on this: >> - Would we need a separate per-core object for core-wide ISA-specific >> state? I'm guessing we might. > > We might. There's no such thing right now that jumps to mind. I remember > there being some ambiguity with SPARC where some state might have been > for all threads in a core. I think we just hope that doesn't get touched > which I think has been true. Ali might remember more what this was > about, but it may have had to do with TLBs and error reporting.
I think this is one of the issues that needs to be given special attention to if the indexer is to work well for both single & multithreaded cases. The example I worry about is the MIPS system registers in the multithreaded case. A number of those registers are per-core and then a number of those registers is per-thread. This makes a per-thread "only" solution a little complicated when your changing state that needs to be core-wide visible. -- ---------- Korey L Sewell Graduate Student - PhD Candidate Computer Science & Engineering University of Michigan _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
