Ok. I figured it was something like that. Rather than use those in place in O3, we might want to try to put them in a neutral spot and then make them available for both. It would probably be confusing for someone working on o3 if they ended up changing in order accidentally in the process. I think generally decoupling o3 a little bit from its innards would be a good thing since it can be hard to move things around in there.
Gabe Quoting Korey Sewell <[email protected]>: > Because things like branch predictors, return address stacks, and > branch target buffers are good for use in a InOrder model. > > And originally, the inorder model (originally called 'mixie') was > something that would work for both inorder and out-of-order models. > It's supposed to be flexible enough that it isnt tied to any style of > pipelining and simply changing the resources that a instruction needs > to obtain would change the style of pipelining. Since M5 already has a > O3 model, then the out of order functionality is no longer required or > desirable for 99% of users. > > On Fri, Feb 20, 2009 at 2:46 PM, Gabriel Michael Black > <[email protected]> wrote: >> Why is the in order model asking for O3 source files to be compiled in >> the first place? >> >> Gabe >> >> Quoting Korey Sewell <[email protected]>: >> >>> changeset 6fd7648e1b8d in /z/repo/m5 >>> details: http://repo.m5sim.org/m5?cmd=changeset;node=6fd7648e1b8d >>> description: >>> Remove unnecessary building of FreeList/RenameMap in InOrder. >>> Clean-up comments and O3 extensions InOrder Thread Context >>> >>> diffstat: >>> >>> 5 files changed, 4 insertions(+), 111 deletions(-) >>> src/arch/mips/regfile.cc | 6 -- >>> src/cpu/inorder/SConscript | 5 - >>> src/cpu/inorder/cpu.hh | 9 --- >>> src/cpu/inorder/thread_context.cc | 93 >>> ------------------------------------- >>> src/cpu/inorder/thread_context.hh | 2 >>> >>> diffs (266 lines): >>> >>> diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/arch/mips/regfile.cc >>> --- a/src/arch/mips/regfile.cc Wed Feb 18 10:00:15 2009 -0800 >>> +++ b/src/arch/mips/regfile.cc Fri Feb 20 11:02:48 2009 -0500 >>> @@ -200,12 +200,6 @@ >>> } >>> >>> void >>> -MipsISA::copyRegs(ThreadContext *src, ThreadContext *dest); >>> -{ >>> - panic("Copy Regs Not Implemented Yet\n"); >>> -} >>> - >>> -void >>> MipsISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest) >>> { >>> panic("Copy Misc. Regs Not Implemented Yet\n"); >>> diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/SConscript >>> --- a/src/cpu/inorder/SConscript Wed Feb 18 10:00:15 2009 -0800 >>> +++ b/src/cpu/inorder/SConscript Fri Feb 20 11:02:48 2009 -0500 >>> @@ -42,13 +42,12 @@ >>> TraceFlag('InOrderCPU') >>> TraceFlag('InOrderMDU') >>> TraceFlag('RegDepMap') >>> - TraceFlag('Rename') >>> TraceFlag('InOrderDynInst') >>> TraceFlag('Resource') >>> TraceFlag('RefCount') >>> >>> CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', >>> 'InOrderCPU', >>> - 'InOrderMDU', 'RegDepMap', 'Resource', 'Rename']) >>> + 'InOrderMDU', 'RegDepMap', 'Resource']) >>> >>> Source('pipeline_traits.cc') >>> Source('inorder_dyn_inst.cc') >>> @@ -74,8 +73,6 @@ >>> Source('../o3/btb.cc') >>> Source('../o3/tournament_pred.cc') >>> Source('../o3/2bit_local_pred.cc') >>> - Source('../o3/free_list.cc') >>> - Source('../o3/rename_map.cc') >>> Source('../o3/ras.cc') >>> Source('thread_context.cc') >>> Source('cpu.cc') >>> diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/cpu.hh >>> --- a/src/cpu/inorder/cpu.hh Wed Feb 18 10:00:15 2009 -0800 >>> +++ b/src/cpu/inorder/cpu.hh Fri Feb 20 11:02:48 2009 -0500 >>> @@ -77,7 +77,6 @@ >>> typedef TheISA::FloatRegBits FloatRegBits; >>> typedef TheISA::MiscReg MiscReg; >>> typedef TheISA::RegFile RegFile; >>> - typedef SimpleRenameMap RenameMap; >>> >>> //DynInstPtr TypeDefs >>> typedef ThePipeline::DynInstPtr DynInstPtr; >>> @@ -586,14 +585,6 @@ >>> >>> std::list<unsigned> fetchPriorityList; >>> >>> - /** Rename Map for architectural-to-physical register mappings. >>> - * In a In-order processor, the mapping is fixed >>> - * (e.g. Thread 1: 0-31, Thread 1: 32-63, etc.) >>> - * In a Out-of-Order processor, this is used to maintain >>> - * sequential consistency (?right word here?). >>> - */ >>> - RenameMap renameMap[ThePipeline::MaxThreads]; >>> - >>> protected: >>> /** Active Threads List */ >>> std::list<unsigned> activeThreads; >>> diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.cc >>> --- a/src/cpu/inorder/thread_context.cc Wed Feb 18 10:00:15 >>> 2009 -0800 >>> +++ b/src/cpu/inorder/thread_context.cc Fri Feb 20 11:02:48 >>> 2009 -0500 >>> @@ -44,7 +44,6 @@ >>> // copy over functional state >>> setStatus(old_context->status()); >>> copyArchRegs(old_context); >>> - //setCpuId(0/*old_context->readCpuId()*/); >>> >>> thread->funcExeInst = old_context->readFuncExeInst(); >>> old_context->setStatus(ThreadContext::Unallocated); >>> @@ -61,18 +60,8 @@ >>> if (thread->status() == ThreadContext::Active) >>> return; >>> >>> - // @TODO: Make this process useful again... >>> - //if (thread->status() == ThreadContext::Unallocated) { >>> - // Allows the CPU to drain partitioned resources >>> - // before inserting thread into the CPU >>> - // (e.g. bind physical registers) >>> - //cpu->activateWhenReady(thread->readTid()); >>> - //return; >>> - //} >>> - >>> thread->setStatus(ThreadContext::Active); >>> >>> - // status() == Suspended >>> cpu->activateContext(thread->readTid(), delay); >>> } >>> >>> @@ -157,37 +146,9 @@ >>> >>> >>> void >>> -InOrderThreadContext::copyArchRegs(ThreadContext *tc) >>> +InOrderThreadContext::copyArchRegs(ThreadContext *src_tc) >>> { >>> - unsigned tid = thread->readTid(); >>> - PhysRegIndex renamed_reg; >>> - >>> - // First loop through the integer registers. >>> - for (int i = 0; i < TheISA::NumIntRegs; ++i) { >>> - renamed_reg = cpu->renameMap[tid].lookup(i); >>> - >>> - DPRINTF(InOrderCPU, "Copying over register %i, had data %lli, " >>> - "now has data %lli.\n", >>> - renamed_reg, cpu->readIntReg(renamed_reg, tid), >>> - tc->readIntReg(i)); >>> - >>> - cpu->setIntReg(renamed_reg, tc->readIntReg(i), tid); >>> - } >>> - >>> - // Then loop through the floating point registers. >>> - for (int i = 0; i < TheISA::NumFloatRegs; ++i) { >>> - renamed_reg = cpu->renameMap[tid].lookup(i + >>> TheISA::FP_Base_DepTag); >>> - cpu->setFloatRegBits(renamed_reg, tc->readFloatRegBits(i), tid); >>> - } >>> - >>> - // Copy the misc regs. >>> - TheISA::copyMiscRegs(tc, this); >>> - >>> - // Then finally set the PC and the next PC. >>> - cpu->setPC(tc->readPC(), tid); >>> - cpu->setNextPC(tc->readNextPC(), tid); >>> - cpu->setNextNPC(tc->readNextNPC(), tid); >>> - this->thread->funcExeInst = tc->readFuncExeInst(); >>> + TheISA::copyRegs(src_tc, this); >>> } >>> >>> >>> @@ -236,33 +197,18 @@ >>> InOrderThreadContext::setIntReg(int reg_idx, uint64_t val) >>> { >>> cpu->setIntReg(reg_idx, val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - // cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val, int width) >>> { >>> cpu->setFloatReg(reg_idx, val, thread->readTid(), width); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> InOrderThreadContext::setFloatReg(int reg_idx, FloatReg val) >>> { >>> cpu->setFloatReg(reg_idx, val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> @@ -270,22 +216,12 @@ >>> int width) >>> { >>> cpu->setFloatRegBits(reg_idx, val, thread->readTid(), width); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> InOrderThreadContext::setFloatRegBits(int reg_idx, FloatRegBits val) >>> { >>> cpu->setFloatRegBits(reg_idx, val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> @@ -299,11 +235,6 @@ >>> { >>> DPRINTF(InOrderCPU, "Setting PC to %08p\n", val); >>> cpu->setPC(val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> @@ -311,11 +242,6 @@ >>> { >>> DPRINTF(InOrderCPU, "Setting NPC to %08p\n", val); >>> cpu->setNextPC(val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> @@ -323,33 +249,18 @@ >>> { >>> DPRINTF(InOrderCPU, "Setting NNPC to %08p\n", val); >>> cpu->setNextNPC(val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> InOrderThreadContext::setMiscRegNoEffect(int misc_reg, const MiscReg &val) >>> { >>> cpu->setMiscRegNoEffect(misc_reg, val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> void >>> InOrderThreadContext::setMiscReg(int misc_reg, const MiscReg &val) >>> { >>> cpu->setMiscReg(misc_reg, val, thread->readTid()); >>> - >>> - // Squash if we're not already in a state update mode. >>> - //if (!thread->trapPending && !thread->inSyscall) { >>> - //cpu->squashFromTC(thread->readTid()); >>> - //} >>> } >>> >>> TheISA::IntReg >>> diff -r e9f9c0f7e5f0 -r 6fd7648e1b8d src/cpu/inorder/thread_context.hh >>> --- a/src/cpu/inorder/thread_context.hh Wed Feb 18 10:00:15 >>> 2009 -0800 >>> +++ b/src/cpu/inorder/thread_context.hh Fri Feb 20 11:02:48 >>> 2009 -0500 >>> @@ -147,7 +147,7 @@ >>> virtual TheISA::MachInst getInst(); >>> >>> /** Copies the architectural registers from another TC into >>> this TC. */ >>> - virtual void copyArchRegs(ThreadContext *tc); >>> + virtual void copyArchRegs(ThreadContext *src_tc); >>> >>> /** Resets all architectural registers to 0. */ >>> virtual void clearArchRegs(); >>> _______________________________________________ >>> m5-dev mailing list >>> [email protected] >>> http://m5sim.org/mailman/listinfo/m5-dev >>> >> >> >> _______________________________________________ >> m5-dev mailing list >> [email protected] >> http://m5sim.org/mailman/listinfo/m5-dev >> > > > > -- > ---------- > Korey L Sewell > Graduate Student - PhD Candidate > Computer Science & Engineering > University of Michigan > _______________________________________________ > m5-dev mailing list > [email protected] > http://m5sim.org/mailman/listinfo/m5-dev > _______________________________________________ m5-dev mailing list [email protected] http://m5sim.org/mailman/listinfo/m5-dev
