changeset a87880065b42 in /z/repo/m5 details: http://repo.m5sim.org/m5?cmd=changeset;node=a87880065b42 description: Remove unused functions/comments cluttering up the code.
diffstat: 13 files changed, 14 insertions(+), 159 deletions(-) src/cpu/inorder/SConscript | 2 - src/cpu/inorder/cpu.cc | 45 +---------------------- src/cpu/inorder/cpu.hh | 25 +------------ src/cpu/inorder/inorder_cpu_builder.cc | 1 src/cpu/inorder/inorder_dyn_inst.cc | 59 +------------------------------ src/cpu/inorder/inorder_dyn_inst.hh | 4 -- src/cpu/inorder/params.hh | 2 - src/cpu/inorder/pipeline_stage.cc | 13 +----- src/cpu/inorder/pipeline_stage.hh | 3 - src/cpu/inorder/pipeline_traits.hh | 7 --- src/cpu/inorder/resource.hh | 3 - src/cpu/inorder/resources/cache_unit.cc | 6 +-- src/cpu/inorder/thread_context.hh | 3 - diffs (truncated from 454 to 300 lines): diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/SConscript --- a/src/cpu/inorder/SConscript Wed Mar 04 13:17:07 2009 -0500 +++ b/src/cpu/inorder/SConscript Wed Mar 04 13:17:08 2009 -0500 @@ -47,7 +47,7 @@ TraceFlag('RefCount') CompoundFlag('InOrderCPUAll', [ 'InOrderStage', 'InOrderStall', 'InOrderCPU', - 'InOrderMDU', 'RegDepMap', 'Resource']) + 'InOrderMDU', 'InOrderCachePort', 'RegDepMap', 'Resource']) Source('pipeline_traits.cc') Source('inorder_dyn_inst.cc') diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/cpu.cc --- a/src/cpu/inorder/cpu.cc Wed Mar 04 13:17:07 2009 -0500 +++ b/src/cpu/inorder/cpu.cc Wed Mar 04 13:17:08 2009 -0500 @@ -46,7 +46,6 @@ #include "cpu/inorder/resource_pool.hh" #include "mem/translating_port.hh" #include "sim/process.hh" -//#include "sim/root.hh" #include "sim/stat_control.hh" #include <algorithm> @@ -162,7 +161,6 @@ cpu_params = params; resPool = new ResourcePool(this, params); -// resPool->init(); coreType = "default"; // eventually get this from params @@ -191,13 +189,9 @@ } - /* Use this port to for syscall emulation writes to memory. */ - //Port *mem_port = NULL; - //TranslatingPort *trans_port = NULL; - for (int i = 0; i < numThreads; ++i) { if (i < params->workload.size()) { - DPRINTF(InOrderCPU, "Workload[%i] process is %#x", + DPRINTF(InOrderCPU, "Workload[%i] process is %#x\n", i, this->thread[i]); this->thread[i] = new Thread(this, i, params->workload[i], i); @@ -208,11 +202,8 @@ } else { //Allocate Empty thread so M5 can use later //when scheduling threads to CPU - Process* dummy_proc = params->workload[0]; //LiveProcess::createDummy(); + Process* dummy_proc = params->workload[0]; this->thread[i] = new Thread(this, i, dummy_proc, i); - - // Set Up Syscall Emulation Port - //this->thread[i]->setMemPort(trans_port); } // Setup the TC that will serve as the interface to the threads/CPU. @@ -790,8 +781,6 @@ { DPRINTF(InOrderCPU,"[tid:%i]: Deallocating ...", tid); - //removeThread(tid); - removeFromCurrentThreads(tid); deactivateThread(tid); @@ -840,19 +829,6 @@ } -void -InOrderCPU::signalSwitched() -{ - panic("Unimplemented Function\n."); -} - - -void -InOrderCPU::takeOverFrom(BaseCPU *oldCPU) -{ - panic("Take Over From Another CPU\n."); -} - uint64_t InOrderCPU::readPC(unsigned tid) { @@ -1205,14 +1181,6 @@ } } -/* - -void -InOrderCPU::removeAllInsts() -{ - instList.clear(); -} -*/ void InOrderCPU::dumpInsts() @@ -1233,14 +1201,6 @@ ++num; } } -/* - -void -InOrderCPU::wakeDependents(DynInstPtr &inst) -{ - iew.wakeDependents(inst); -} -*/ void InOrderCPU::wakeCPU() @@ -1252,6 +1212,7 @@ DPRINTF(Activity, "Waking up CPU\n"); + //@todo: figure out how to count idleCycles correctly //idleCycles += (curTick - 1) - lastRunningCycle; mainEventQueue.schedule(&tickEvent, curTick); diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/cpu.hh --- a/src/cpu/inorder/cpu.hh Wed Mar 04 13:17:07 2009 -0500 +++ b/src/cpu/inorder/cpu.hh Wed Mar 04 13:17:08 2009 -0500 @@ -249,9 +249,6 @@ TheISA::IntReg nextNPC[ThePipeline::MaxThreads]; /** The Register File for the CPU */ - /** @TODO: This regFile wont be a sufficient solution for out-of-order, add register - * files as a resource in order to handle ths problem - */ TheISA::IntRegFile intRegFile[ThePipeline::MaxThreads];; TheISA::FloatRegFile floatRegFile[ThePipeline::MaxThreads];; TheISA::MiscRegFile miscRegFile; @@ -362,15 +359,6 @@ void switchToActive(int stage_idx) { /*pipelineStage[stage_idx]->switchToActive();*/ } - /** Switches out this CPU. (Unused currently) */ - //void switchOut(Sampler *sampler); - - /** Signals to this CPU that a stage has completed switching out. (Unused currently)*/ - void signalSwitched(); - - /** Takes over from another CPU. (Unused currently)*/ - void takeOverFrom(BaseCPU *oldCPU); - /** Get the current instruction sequence number, and increment it. */ InstSeqNum getAndIncrementInstSeq(unsigned tid) { return globalSeqNum[tid]++; } @@ -389,6 +377,7 @@ globalSeqNum[tid] = seq_num; } + /** Get & Update Next Event Number */ InstSeqNum getNextEventNum() { return cpuEventNum++; @@ -463,9 +452,6 @@ /** Sets the next NPC of a specific thread. */ void setNextNPC(uint64_t val, unsigned tid); - /** Add Destination Register To Dependency Maps */ - //void addToRegDepMap(DynInstPtr &inst); - /** Function to add instruction onto the head of the list of the * instructions. Used when new instructions are fetched. */ @@ -530,13 +516,6 @@ */ std::queue<Event*> cpuEventRemoveList; -#ifdef DEBUG - /** Debug structure to keep track of the sequence numbers still in - * flight. - */ - std::set<InstSeqNum> snList; -#endif - /** Records if instructions need to be removed this cycle due to * being retired or squashed. */ @@ -610,7 +589,6 @@ unsigned readStCondFailures() { return stCondFails; } unsigned setStCondFailures(unsigned st_fails) { return stCondFails = st_fails; } - public: /** Returns a pointer to a thread context. */ ThreadContext *tcBase(unsigned tid = 0) { @@ -631,6 +609,7 @@ /** Pointer to the icache interface. */ MemInterface *icacheInterface; + /** Pointer to the dcache interface. */ MemInterface *dcacheInterface; diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/inorder_cpu_builder.cc --- a/src/cpu/inorder/inorder_cpu_builder.cc Wed Mar 04 13:17:07 2009 -0500 +++ b/src/cpu/inorder/inorder_cpu_builder.cc Wed Mar 04 13:17:08 2009 -0500 @@ -35,7 +35,6 @@ #include "cpu/inst_seq.hh" #include "cpu/static_inst.hh" #include "cpu/inorder/cpu.hh" -//#include "cpu/inorder/params.hh" #include "cpu/inorder/inorder_dyn_inst.hh" #include "cpu/inorder/pipeline_traits.hh" #include "params/InOrderCPU.hh" diff -r a6d07755d34f -r a87880065b42 src/cpu/inorder/inorder_dyn_inst.cc --- a/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 13:17:07 2009 -0500 +++ b/src/cpu/inorder/inorder_dyn_inst.cc Wed Mar 04 13:17:08 2009 -0500 @@ -167,10 +167,6 @@ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction created. (active insts: %i)\n", threadNumber, seqNum, instcount); - -#ifdef DEBUG - cpu->snList.insert(seqNum); -#endif } @@ -192,9 +188,6 @@ DPRINTF(InOrderDynInst, "DynInst: [tid:%i] [sn:%lli] Instruction destroyed. (active insts: %i)\n", threadNumber, seqNum, instcount); -#ifdef DEBUG - cpu->snList.erase(seqNum); -#endif } void @@ -305,44 +298,13 @@ void InOrderDynInst::prefetch(Addr addr, unsigned flags) { - // This is the "functional" implementation of prefetch. Not much - // happens here since prefetches don't affect the architectural - // state. -/* - // Generate a MemReq so we can translate the effective address. - MemReqPtr req = new MemReq(addr, thread->getXCProxy(), 1, flags); - req->asid = asid; - - // Prefetches never cause faults. - fault = NoFault; - - // note this is a local, not InOrderDynInst::fault - Fault trans_fault = cpu->translateDataReadReq(req); - - if (trans_fault == NoFault && !(req->flags & UNCACHEABLE)) { - // It's a valid address to cacheable space. Record key MemReq - // parameters so we can generate another one just like it for - // the timing access without calling translate() again (which - // might mess up the TLB). - effAddr = req->vaddr; - physEffAddr = req->paddr; - memReqFlags = req->flags; - } else { - // Bogus address (invalid or uncacheable space). Mark it by - // setting the eff_addr to InvalidAddr. - effAddr = physEffAddr = MemReq::inval_addr; - } - - if (traceData) { - traceData->setAddr(addr); - } -*/ + panic("Prefetch Unimplemented\n"); } void InOrderDynInst::writeHint(Addr addr, int size, unsigned flags) { - // Not currently supported. + panic("Write-Hint Unimplemented\n"); } /** @@ -762,20 +724,3 @@ my_hash_t thishash; #endif - -#ifdef DEBUG - -void -InOrderDynInst::dumpSNList() -{ - std::set<InstSeqNum>::iterator sn_it = cpu->snList.begin(); - - int count = 0; - while (sn_it != cpu->snList.end()) { - cprintf("%i: [sn:%lli] not destroyed\n", count, (*sn_it)); _______________________________________________ m5-dev mailing list m5-dev@m5sim.org http://m5sim.org/mailman/listinfo/m5-dev